Senior Hardware Engineer Resume Sunnyvale, CA - Hire IT People

OBJECTIVE:

Seeking a position in Physical Design or RTL Synthesis - Physical Design Automation including RTL to layout/GDSII, RTL synthesis and place and route scripting, STA, timing closure, performance-power-area optimization, design capture, verification.

TECHNICAL SKILLS:

CAD Tools: Synopsys DC/DC-Topographical/DFT Compiler/PT/Hercules, Magma Talus/Hydra, Cadence ICFB, Assura, Mentor Graphic Calibre, Synopsys Star RC-XT, Formality, Nanosim, Magma FineSimComputer Languages: TCL, Verilog, C

PROFESSIONAL EXPERIENCE:

Confidential, Sunnyvale, CA

Senior Hardware Engineer

Responsibilities:

Developed and executed CAD automation platform/flow/methodology for RTLSynthesis/Physical Design for TSMC40/65/90nm. Developed TCL automation scripts to execute RTL-GDSII flow and implemented synthesis/P&R.
Synthesized RTL netlist in Synopsys DC/DC Topographical with scan insertion/clock-gating. Performed PPA optimization and STA.
Implemented floor planning and block partitioning. Placed and routed standard-cell/soft-macros (partitions)/hard-macros. Analyzed and fixed congestion in Magma Talus Hydra.
Implemented power planning using Magma Talus Power Pro and clock tree synthesis using Magma Talus Design.
Performed DRC/LVS in Talus Design/Synopsys Hercules and fixed DRC errors.
Performed timing closure in Synopsys PT with extracted RC Spef from Talus Design.
LTE UE PHY for MIMOon: Implemented the RTL synthesis and physical design in TSMC-CLN40G with 149603 standard cells/171 memory hard-macros/9 partitions, 870-MHz clock and 5.9mm x 5.9mm dice size.
Transceiver for Algotochip: Implemented the RTL synthesis and physical design in TSMC-CLN40G with 107201 standard cells/31 memory hard-macros/3 partitions, 500-MHz clock and 3.5mm x 3.5mm dice size.
Jpeg Image Processor for Nvidia: Implemented the RTL synthesis and physical design in TSMC-CLN40G with 81730 standard cells, 384-MHz clock and .432mm x .432mm dice size.

Confidential, San Jose, CA

Senior Digital-Mixed Signal IC Designer/Consultant

Responsibilities:

work included 900MHz-Direct Digital Frequency Synthesizer's RTL-synthesis, digital IC design and spurious frequency analysis for Digital Down Conversion with low -90-dbc spur in Sony 65nm CMOS process. work included PLL system/block characterization (Matlab/Verilog-A), phase noise and spurious frequency analysis,RTL-synthesis and digital IC design for 1.8GHz 3rd order Delta Sigma Fractional-N PLL achieved -86dBc in-band phase noise and -80-dbc spur in Sony 65nm CMOS process.

Confidential, San Jose, CA

Senior Digital-Mixed Signal IC Design Engineer

Responsibilities:

4th Order Delta-Sigma Fractional-N PLL in STMicro 0.13um HCMOS9 process: 2.4GHz low in-band phase noise ( -101dBc) for wide loop BW (240KHz). 5.0GHz low in-band phase noise (-97dBc) for wide loop BW (240KHz). Digital core area: 450um x 470um
3rd Order Area-Saving Delta-Sigma and Loop Filter-less Fractional-N PLL in SONY 90-nm CMOS process: 2.15GHz low in-band phase noise (-100dBc) for wide loop BW (420KHz). Digital core area: 100um x 500um.
Direct Digital Frequency Synthesizer (DDFS) for SAW filter-less Digital Down Conversion (DDC) Front-End 0.04-2.15GHz Digital TV tuner in SONY 90-nm CMOS process including: 700MHz-Merged-CORDIC DDFS for 1KHz resolution, < 70-dBc SFDR, <100-ns phase switching.

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Senior Hardware Engineer Resume

Sunnyvale, CA

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