OBJECTIVE:

• To be a part of VLSI design/verification team and passion to perform.

SUMMARY:

• Worked on verification of SSD flash controller, storage chips, TCP offload engine, Analog Devices processors, ARM based SoCs and Ethernet based SoCs.
• Expert in UVM/VMM/SV/C/C++ based verification.
• Performed development of golden models C/C++, System Verilog and Verilog
• Functional Coverage models and Code Coverage analysis
• Developed System Verilog Assertions
• Performed block level and system level verification
• Performed RTL Coding and equivalency check
• Post silicon Validation
• Emulation using Palladium
• Expert in script development
• Verification infrastructure development, tool developments, linting checks, License Model development
• Technical mentorship, hiring and
• Presented technical paper at client’s forum (Vidyuth at AMD India) and published.
• Received of appreciation from former Indian presidential candidate. Received a for good score in general knowledge test conducted at state level (India). Participated in various competitions in school and college level quiz and debate competition. History of prizes in quiz, debate and elocution competition.

TECHNICAL SKILLS:

Hardware Verification Language: System Verilog (UVM and VMM), VERA.

Hardware Description Language: Verilog and VHDL.

Special Tools: Common Power Format (CPF), CoverCheck and Autocheck

High Level Language: C, C++.

Protocols: PCIe, ONFI, AMBA AHB/AXI, OCP, Serial Peripheral Interface (SPI), I2C, AR INC 661, AR INC 708, Internet Small Computer Systems Interface (iSCSI), MPA.

Assembly Language: Analog Devices Black Fin and Shark (2116x), Intel s 8085, 8086 p and 8051 c.

Scripting and other Languages: PERL, TCL, SHELL, Python, MySQL, XML and YML

Repository Management Tools: Git, P4, SVN and CVS.

Linting Tools: Insure++ and Purify.

PROFESSIONAL EXPERIENCE:

Confidential

Responsibilities:

• Block level verification of fabric performance measurement unit using SV UVM(HoloLens)
• Verification of SPI, Ring Oscillator (Analog design), Junction Temperature Monitor (Analog module), Debug & Cross trigger on Tensilica based processor based SoC using C(HoloLens)
• JTAG based debug tool development for emulation and post - silicon validation
• Post-silicon validation of SoC for HoloLens.
• Emulation of SoC for HoloLens using palladium

Confidential

Responsibilities:

• ARM based SSD flash controller verification. Low power verification using CPF.
• ONFI test cases development and debugging.
• Writing soft reset and ECC test cases and debugging.
• Generating ATE stimulus through JTAG interface.
• Developing and debugging ARM DSM based tests.

Confidential

Responsibilities:

• ONFI VIP development in SV UVM.
• SATA test plan development

Confidential

Responsibilities:

• Verification of Weather Radar/Terrain: Contributed towards test cases development, procedures and traceability. model development in System Verilog.
• Worked on improving code coverage.

Confidential

Responsibilities:

• Verification of NANDc and LCDc: Technically leading verification activity. Test bench architecture update, test plan development. Test bench coding and test case development in VERA.
• Power Aware Verification: Power aware verification environment development in Common Power Format (CPF).
• SV-UVM Template Standardization for In-house VIP
• Globalization of Regression Language Compiler (RLC): RLC is tool developed in PERL which dispatches simulation jobs in batches.
• Verification Infrastructure Development for Core and SoC Project: Project bring up from verification infrastructure point of view, involves tools/flow bring up. Development of internal tools.
• Linting checks using Insure++ and Purify: Check any irregularities like memory leakage, memory corruption, reading null pointer etc. components developed in C++.
• Tool Development: Developed the global tool to monitor the code changes in RTL files & verification, tools for branch management and revision monitoring for various kinds of environment. Developed miscellaneous tools.
• Hiring and at client place.
• Miscellaneous: Mentoring APB VIP(UVM) standardization. Mentoring Process controller verification. License model development using Flexnet Publisher. Siloti analysis for improving dump time. VCS parallel dump for simulation performance improvement:

Confidential

Responsibilities:

• Built verification environment for PCIe Host side modules for Converged Network Adaptor (ARM Based SoC).
• System Verilog with Verification Methodology Manual (VMM) was used for the development of Verification environment.
• Developed golden model ( model) in PCIe Transmit Engine and Hardware Offload Engine Expander for Host Bus Adapter and Converged Network Adaptor using C++.

Confidential

Responsibilities:

• Verification of CPUDMA, an engine to manage DMA descriptor on receive path and transmit path of the 2-Giga bits and 10-Giga bits Ethernet based TCP offload engine.
• Ownership of flash interface and management microcontroller (I2C) functional issue resolution.
• Verified Marker-based Protocol Data Unit Alignment (MPA).
• Developed basic verification environment for Internet Small Computer Systems Interface (iSCSI).

Confidential

Responsibilities:

• Involved in building and managing verification team to meet clients’ requirements.
• Technical mentor for VERA

Confidential

Responsibilities:

• Development and validation of Random Test Generator (RTG): Developed RTG for Digital Signal Processor (Blackfin) core, DMA and instruction coverage for core in VERA.
• RTG interface to Silicon and debugging test cases (Post Silicon Verification): RTG Test cases are run on C model to get self-checking tests. Self-checking tests are converted to Visual DSP compatible format tests, which are directly run on silicon (EZ-KIT BF-561) through TCL script. The entire process is automated in PERL.
• RTL Coding and Equivalence check for Blackfin DSP: RTL is written by looking at the schematic of the blocks. To check the correctness of the RTL, equivalence checking is performed between RTL and available net list using Chrysalis.
• Functional Issue Debugging: Work around for the functional issues related to Serial Peripheral Interface (SPI) and Serial Port (SP) of 2116x DSP. Task involves understanding the issue, related test cases and providing solution. Test cases are available in assembly language
• Yield Debugging of 2116x DSP: Yield debugging involves detection of fabrication defects by analyzing the failure patterns. Failure pattern of the chip and the pattern produced by running net list with error injected in to suspected node are matched. Pattern matching reveals whether the suspected node is faulty.
• Miscellaneous: Modifying simulation scripts in PERL and SHELL to use different memory and directory structure for the results of the simulation to enhance debugging and readability of the output files.

Confidential

Responsibilities:

• Designing encryption, decryption, code converters and timer circuits for use in the in house projects.
• Verifying the RF synthesizer and power supply operations.