Design Engineer Resume Franklin Park - Hire IT People

SUMMARY:

Programmed a simulator in C++ for computers connected in a network that can generate datagrams and pass them from one machine in the network to other machines
Developed a Python based tool suite Used machine learning techniques like data regression and classification to accomplish data processing features like face detection, cross validation
Studied basics of memory allocation and management, synchronization primitives for kernel interfaces and methods
Designed soft error emulation framework tested on 16 - bit floating point adder
RTL Design, static timing analysis and constraint methodology implementation
Studied soft errors at various levels (software, architecture, micro-architecture, flip-flop) and designed correction measures
Validate functional equivalence between the software model and RTL using Xilinx Microblaze

TECHNICAL SKILLS:

Technology and Tools: C/C++, Python, Perl, Linux, Unix VHDL, Verilog, Assembly language, MATLAB Gem5, Cadence Virtuoso, Mentor Graphics Calibre DRC/LVS, Cadence ADE XL Modelsim, Quartus, Synopsys Cosmoscope, PSpice, ClearCase, Git, Bash

WORK EXPERIENCE:

Confidential, Franklin Park

Design Engineer

Responsibilities:

Design, logic synthesis, timing & power analysis for embedded memories
Developed C++ real-time firmware modules for cross-platform performance and functionality of ARM MCU
Programmed C++ libraries for network communication using existing networking protocols concepts (TCP/IP, UDP) and PCI Express
Perform verification and validation to verify HW and BSP on changes, setup device drivers and interact with Linux kernel

Confidential

Physical Design Engineer

Responsibilities:

Optimize, verify and debug transistor-level circuit of superconducting memory device for spin switch effects characterization
Developed and optimized C++ algorithms to meet stringent memory and cycle budgets on target hardware
Structured VLSI Design, physical layout blocks, verification support throughout design cycle
Python scripting for process automation
High Performance C++ software testing for single instruction multiple data paradigm on Linux platform

Confidential

Systems Researcher

Responsibilities:

Developed FPGA Streaming Architecture Stereo Audio DSP with UDP Parser and Writer on Altera NIOS
Designed and developed C++ advanced software modules that follow modern design patterns.
Implemented architecture as CAD structure for the design analysis
Employed strategies including use of packages and generics, loop unrolling, pipelining, and fixed-point arithmetic block design

Confidential

MIPS Processor

Responsibilities:

Developed in C and VHDL a single-cycle processor that can handle arithmetic, conditional, logical instructions of MIPS instruction set with forwarding and hazard-elimination
Designed and developed caches in C and VHDL with parameters including block size, capacity, associativity, write, allocation and replacement policy
Using C++ and Gem5, simulated x86 ISA employing MESI write-back invalidation protocol under different cache configurations
Studied performances of multithreaded SPLASH-2 benchmarks using measured cache miss rates and bus traffic
Implemented the RTL Design using Verilog-2000 HDL in ModelSim
Synthesized the code using Cadence RTL Compiler to acquire the netlist
Generated the layout using Cadence SoC Encounter and Performed Static Timing Analysis using PrimeTime SI
Performed functional Verification on the generated GDS file

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Design Engineer Resume

Franklin, ParK

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