SUMMARY:

• Over 10 years of experience in
• HW Product design and development - Schematic Design, PCB and architecture High-speed and Mixed signal, flex board design - Compliances and product s Board Bring up, testing, debugging - Manufacturing, Automation test Engineering documentation - Modeling, pre & Post layout SI & EMI/EMC simulations Wearable / ARM&MIPS Semi-conductor silicon / Server / Mobile / Multimedia / Tablet / Telecom Confidential
• Experience in HW Design/Development/Verification and Validation of Multicore/Multithread MIPS/ARM Server based architecture in Semiconductor industry
• Complex 10G/25G SERDES, Multi Node 800W Server based design and bring up
• Cross functional team experience and proven track record of bringing products to market.
• Proficient in Hardware product Life Cycle Developments
• Experience in establishing vendor network & interactions with the clients and partners.
• Mapping requirements and Providing best Confidential involving evaluation and definition of scope of project and finalization of project requirements
• Implementing project plans, work break down structures
• Effort and cost estimation and Optimization
• Resource planning and setting up communication channels across the organization

TECHNICAL SKILLS:

Design/PCB CAD tools: Cadence Capture CIS, Allegro PCB Design Expert, Altium Designer and Concept HDL

Simulation tools: Code Composer Studio, Altera FPGA Quartus II, Hyperlynx and LTspice

Processor/Controller: XLP9xx, XLP5xx, BCM516xx, Qualcomm Snapdragon 805, OMAP5, OMAP4, TMS320DM8148, TMS320DM8168, MPC8360 & MSC8144, PXA270, STM32F217VE, MSP430 and AT91SAM9G20 Micro controllerFPGAs: Xilinx, Altera

Interfaces/ Topologies: PCIe Gen3, ICI and USB 3.0 SERDES, Multimedia Based design - SD,HD Video Codec (Analog & Digital), McASP, Multiple Camera & LCD (CSI and Parallel) with Touch screen, HDMI, Battery Charger with fuel gauge, Ethernet interface, WLAN/BT Interface, GSM, GPS, USB2.0,3.0 & OTG, PCI, PCI-e, SIM card Interface, UART, I2C, SPI,CAN, E1/T1/J1 Telecom

Memories: DDR4/3/2, POP, EEPROM, NAND, NOR, SDRAM, MMC, eMMC, SSD

Power supply and others: Intel VR based VRM, PMIC, Multi-phase, DC-DC Power regulators & Module, LDO

Tools: /Equipment: CRO & DSO, Logic analyzer, Spectrum analyzer, Blackhawk & BDI Emulator, HDMI Analyzer, Generic test, Protocol Analyzer and measure Equipment, PCIe, USB Protocol Analyzer

Languages: Assembly, gel scripts for OMAP, C

PROFESSIONAL EXPERIENCE:

Confidential, Santa Clara, CA

Senior Design Engineer

Responsibilities:

• Handled various HW Validation Platform for upcoming ARM Multi core Server-Class processor
• Board Design / Bring up pre-silicon and post silicon testing
• Silicon Verification/Validation of PCIe Gen3, ICI, USB3.0, SATA SERDES with cross functional team
• Designed Two Socket with BCM516xx Silicon for High speed server management system with 8 Channel DDR4, external PCIe EP, BMC, 800W chassis
• Designed and tested Intel VR based Multi-Phase VRM for High current Core/ Mem/ SOC rails (Max 200W TDP)
• Interface validations/bring up like NOR/NAND/MMC/SPI boot device memories
• Support of MIPS networking processor design and testing including various serdes XAUI/RXAUI/KR/XFI/SGMII

Confidential, Santa Clara, CA

Project Lead

Responsibilities:

• Qualcomm Snapdragon APQ8084 Based wearable glass design.
• Proto DVT,PVT Schematics design, Mechanical ID design interaction, Flex cable design
• HW Bring up and testing of PMIC/WiFi/BT/GPS/Audio/CSI-2/MIPI DSI/Sensors/Dual Battery/Power Supply design.
• Manufacturing & Automation Test builder, production support.
• Design Validation & Verification (WiFI, Battery, Power), Power & Thermal optimization
• ARM AM335 based Robotics vacuum cleaner DVT, PVT and Automated Test jig system Design, Bring up and testing.
• EMI/EMC Lab support and Developed Test Fixture Hardware for Automated Test Plan for Mass production
• Involved in Design and Bring-up of an intrinsically safe ATEX certified Mobile platform based on Intel’s PXA270 processor.
• Board Bring-up with testing of Keypad interface using MSP430 emulator, GPS and GSM, WiFi Module section
• Fuel gauge programming and Power optimization for better Battery Power Management system
• BSP porting, Failure board debugging, Board rework, Gerber generation and verification.
• Board Rework like Soldering & De-soldering components for simple board assembly
• Involved in Project proposal preparation and cost budgeting of the Interceptor Wireless scanner built around ST ARM9 processor, Lantronix P1 module, TI MSP430 and TI OMAP3530.
• Extensive Experience of working with external design teams and consultants (F/W, S/W, PCB Layout, FPGA)

Confidential

Module Lead

Responsibilities:

• Designed, developed, tested and delivered TMS320DM8148 EVM and its application boards for developing Multimedia based DEMO applications
• Developed Engineering specification, Schematic capture, Test Plan and SI analysis of DDR3,Parallel Camera,BT.1120 Video signal for Application board of DM8148-EVM
• Designed, developed, tested and delivered TMS320DM8168 based conduction cooled XMC card for Un-manned vehicle for Avionics
• Board Bring up by coordinating Altera FPGA with BSP team for various interfaces in XMC form factor high dense board
• Signal integrity & Power Analysis and Layout guide line document preparation, Schematic capture, CAD review, Thermal, Power, Mechanical, Weight Analysis for XMC board
• Coordinating with the software and QA teams in solving the system level issues and releasing finished device to production
• Lead a team in developing, testing, integrating the hardware system and resolving the system related issues collaborating with the software and QA teams.
• Trained and assisted the contract manufacturer in building the biometric system by developing the MPI documents.
• System architecture and design Confidential including partitioning hardware/software/FPGA trade-offs and quantitative performance evolutions.
• High speed and mixed signal hardware design and generating circuit schematics
• Component selection, BOM optimization
• Board bring-up and testing of complex PC boards with a combination of high component density, high speeds, and tight timing constraints.
• Created Engineering documentation and hardware functional specifications and test plans for the hardware environment, and overseeing its execution.
• Performing physical measurements, data collection and design validation and simulation correlations.
• Exposure in EMI/EMC, thermal design and DFT/DFM requirements from the system point of view.
• Modelling and Simulations, performing Timing, pre and post layout Signal integrity, thermal, Power budgeting, decoupling capacitor and current density.
• Layer stack up design and working closely with and PCB CAD/layout department to develop the PCB design and optimizations.
• Experience Pre compliance testing and product s (FCC Part 15).
• Working with cross functional teams and managing vendors/distributors.
• Handling all generic Test equipment and standard specific equipment.
• Assembly house and Fab house for proto or protection level support & deliveries
• OMAP5 Experience in TI-Dallas office
• Involved in Schematic Design and CAD review for OMAP5432 and OMAP5430 Tablet main EVM board and side boards like Camera boards, Antenna boards, and Button boards
• Interacting with BSP team for interface validation like Audio, Camera & sensors
• Involved in HDMI validation and, Power and thermal validation for OMAP5 EVM
• Involved in board bring-up and LINUX BSP porting on system built around OMAP5 EVM
• Written diagnostic codes for testing the peripheral interfaces on the devices.
• Debugging and fixing the failure OMAP4 and OMAP5 EVM boards

Confidential

Senior Design Engineer

Responsibilities:

• Designed & Developed 16" Rack Server hardware for Media Gateway in application of Interactive Voice Response System (IVRS) based on MPC8360 networking processor
• Designed PCI and PCI Express based Add-on card for E1/T1 interface using Altium designer.
• Exposure In layer stack-up designing, Foot print creation and Layout guidelines document preparation
• Involved in Board Bring-up and functionality testing support for proto build.
• Knowledge on DFM/DFT based design and level 0 FPGA coding verification.

Confidential

Hardware Engineer

Responsibilities:

• Performed Schematic capture, Component selection and Co-ordinated with CAD team PCB Layout, Pre-route and post-route signal integrity analysis
• ORCAD symbol and foot print creation. Done PCB CAD till Pre Gerber generation.
• Created the Engineering specification and Test plans based on the customer’s high level project requirements
• Experience in high speed Hardware design up to 14 layers involving DDR2 memory and PCI Express and AMCC PowerPC processor.
• Assisted software team during bring-up for Linux Board Support Package (BSP) as part of project deliverable