SUMMARY:

• Systems Engineer, Software Integration Engineer, System Hardware and Software Design EngineerSystem Verification and Test Engineer, and System / Hardware / Software Architect.

PROFESSIONAL EXPERIENCE:

ASIC Design Verification Simulation Engineer

Confidential, North Andover, MA and Allentown, PA

Responsibilities:

• ASIC Verification of the SuperMapper ASIC, a SONET STS - 1 Mapped to T1/E1, DS2, DS3 and Multiple Standard and Custom
• System Interfaces for large scale TELCO Switching Platform Access. Tasks included developing ASIC Verification Operations
• Flow for ASIC RTL Development, Test bench Driver Development in the MTI Simulation Environment, ASIC Verification
• Operations Development, Test Plan Development, Verification Operations Perl Script Development, and ASIC Verification Team Development. Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification

Verilog ASIC Design Verification Simulation Engineer

Confidential, Acton, MA

Responsibilities:

• Verilog ASIC Design Verification of Frame Relay over DS3 ASIC Chipset with Channelized/Unchannelized T1/E1/T3E3. ASIC
• Verification Simulations were executed on the T1/E1/T3/E3 ASIC and the Frame Memory Contoller ASIC which provisioned eight Frame Relay Service Tiers via an ATM Core Switching Hub. Developed T1/E1/T3/E3 Framer Transactor and Design
• Verification Strategy/ Framework developed for Standalone ASIC-Level Testbenches, ASIC Chipset/System-Level Verification.
• Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.

Verilog ASIC Design Verification Simulation Engineer

Confidential, Maynard, MA

Responsibilities:

• Verilog ASIC Design Verification of DEC/Compaq’s next generation Enterprise Server Chipset. ASIC Verification Simulations were executed on the I/O Spanner ASICs which facilitated the data exchange between the multiprocessor server chipset switch fabric and standard PCI Bus ASICs. Standalone ASIC verification and multiprocessor block (18 ASICs) verification testbeds were developed using verilog VCS, verilog PLI, and Perl Scripts. The Enterprise Server Chipset I/O Spanner block contained the following basic functions: Cached DMA, Cache Coherency State Machines, Multiprocessor Switch Fabric Bus Command
• Arbitration State Machines, PCI ASIC I/O Command FSMs, TLB Logic, System Interrupts, and I/O CSRs. Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.

Verilog ASIC and Board Hardware Design Verification Simulation Engineer

Confidential, Rochester, New Hampshire

Responsibilities:

• Simulation Environments were developed on Sparc20 Workstations using verilog modules, perl scripts, SignalScan and Virsim
• Waveform GUIs to verify ASIC Chipset and Board-Level Design Functionality. The PCB/System Level Verilog Netlist consists of 17 ASICs from the 5-ASIC ATM Switch Fabric Chipset, their associated Sync RAM and Async RAM Memory Subsystems, an ATM SAR Chip and Intel I960 Processor, 155 MBPS and 622 MBPS NIC PHY Layer Chips, XILINX FPGA, and Lattice CPLD verilog models. I developed the design verification environment and performed chipset-level system simulations. Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.

Hardware Design Verification and Board Power-Up and Debug Engineer

Confidential, Coral Springs, FL

Responsibilities:

• Substation Three Phase Voltage and Current Fault Signature Detection to localize Power Transmission and Distribution Network
• Power Outages/Brown - Outs. On this embedded systems development project, many tasks were performed using Motorola
• Background Debug Mode with various 68360 Emulators to download SIM register settings and verify/exercise all board

Confidential

Hardware Design and Verification Engineer

Responsibilities:

• Independent ASIC Design & Product-Level Hardware Design Cycle Tools, Methodology, Process Study (1993)
• Independent study to develop detailed knowledge of tools, methodologies, high-level design flow, and hardware verification frameworks for reducing time-to-market, NRE costs, and tool capital requirements. Design process included ASIC, ASIC Chipset, Off-the-Shelf Chips and optimizing design flow to deliver high end products to Telecommunications and Corporate Enterprise Market Customers. Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.

Hardware/Software Test Development Engineer

Confidential, Middletown, RI

Responsibilities:

• Developed software test plans and test scenarios for guidance and control system software modules and PM/FL software algorithms. Expertise developed on system design bug or hazard analysis methodology.

Hardware Design Verification Simulation Engineer / Test Engineer

Confidential, Portsmouth, RI

Responsibilities:

• Hardware Design Verification Simulations were executed for 27 PCB/SMT Board Designs in Hardware Design Engineering.
• Developed verilog models for board level design netlist components. Developed board level design verification tests. Leadership in organizing and documenting methodology for test development team. Functional and Parametric Tests were developed to exercise all module functions and performance requirements. Fault localization test patterns were developed to optimize diagnostic test fault coverage. Fault injection signatures were captured during simulation for stuck-at-one/stuck-at-zero device and I/O faults to speed board fault localization. Device I/O and Netlist I/O states were captured for each clock to automate fault localization when the board simulations were postprocessed to Teradyne, GenRad, LTX, and PC based Test Stations utilizing bject-oriented data structures implementing fault-localization and fault signature methods for electronic systems validation and manufacturing test operations. Designs Validated include communications waveform synthesis, modulation, and demodulation.Expertise in IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.

Systems Design, Test, and Integration Engineer

Confidential, Bedford, MA

Responsibilities:

• Performed Systems Engineering analysis tasks to integrate submarine weapon systems to combat control system for US Navy Submarines. Executed submarine weapon system requirements analysis and documentation for pre-launch, launch, and post-launch signals, events, data at the interface of the combat system and weapon systems.