SUMMARY:

• Over 18 years of effective experience in hardware and firmware design and development with demonstrated s.
• Expert in high speed, high density FPGA, digital ASIC and CMOS design, development, simulation and verification.
• Extensive experience and familiarity with a wide variety of hardware and software development tools, analog and digital circuits and components, schematic and layout tools, RTL development and synthesis IDEs and CMOS layout tools.
• Expert in complex electronics circuits and board design, circuit simulation, prototype, system bring - up, debug and test.
• Proficiency and skills in Microsoft Office (Word, Excel, PowerPoint, Outlook).
• Strong organizational skills and attention to details. Professional attitude and demeanor.
• Ability to multi-task in a fast-paced environment.
• Strong verbal, written, computer and technical communications.
• Ability to work independently and as a team member.
• Versatility and flexibility to work within constantly changing priorities with enthusiasm.
• Thorough understanding of products and equipment, engineering concepts and practices.

TECHNICAL SKILLS:

Development tools: I have designed and developed high density FPGA logic circuits using the following tools and IDEs: Xilinx tools: ISE, PlanAhead, Vivado, iMPACT, PACE, Coregen, ChipScope, PinPlanner. Altera tools: Quartus II 10.1, SOPC Builder, Qsys, MegaWizard PLL gen., SignalTap, Component Editor. Lattice tools: ispLEVER, Diamond. Misc tools: ModelSim PE6.5, SynplifyPro, Simulate, Stimulus Editor and Viewer, Emacs editor. I have performed RTL Synthesis, Testbench development, timing analysis, emulation, debugging, simulation, verification, and worked with V-Metro modules, ucf, qsf, SFL (Serial Flash Loader), Altera Avalon I/F and bus system.

Hardware languages: Extensive familiarity and experience with VHDL, Verilog and TCL (Tool Command Language) scripts.

FPGAs: Experience with Altera Cyclone IV GXB, Stratus, Flex10K, Xilinx Virtex V/IV, Spartan 6/3, Lattice Mach4000, as well as CPLD, PAL, GAL and EPCS configuration FLASH.

Circuit design tools: Altium Designer, ORCAD Sch. Capture and Layout, Pspice, PADS, PCAD, LTSpice.

Hardware components: I have worked with a wide variety of electronic components, transducers and sensors including: MOSFET, Tyristor, Triac, Thermopile Laser sensor, Zener, Laser, LED and PIN diodes, Thermocouple, Optocoupler, CMOS and FET transistors, LDO, voltage regulators and switching supplies, Piezoelectric and Hall sensor, GMR, OpAmps

Hardware interfaces and communication techniques: USB PHY, RFCB (RF Control Bus), LVDS, I2C, SPI, Camera Link, Ethernet, PCI Express, EtherCAT, DSP, PLL, VCO, DDR, ADC, DAC.

Lab tools: Tektronix and HP logic analyzer, Infiniium digital oscilloscope, spectrum analyzer, power analyzer, Signum JTAGJET, AVR JTAGICE, IAR jlink, Xilinx JTAG, Confidential CDP.

PROFESSIONAL EXPERIENCE:

Senior Electrical Engineer

Confidential, Carlsbad, CA

Responsibilities:

• Designed and Developed control board circuits in Altium Designer 15, including both layout and schematic circuits such as: USB 2.0 ULPI PHY HOST controller, USB HUB, Ethernet I/F, OMAP, DVI and HDMI interfaces and control circuits, EEPROM SPI and I2C interfaces, FLASH memory, LPDDR SDRAM, UART, ESD Filters and Level Translation solutions, LDO and Buck Regulators. Worked with QuestaSim, ModelSim, Quartus, Virtex-7, and Office Tools.
• Proficient and skilled in very details of Altium IDE tool suite. Generated Fab and Assembly output files, and documented them in Agile system.
• Troubleshooting root cause of failures as in JIRA tasks. Participated in design reviews and meetings.
• Passed many medical devices s as well as FDA courses and received many s.
• Loaded and configured BL (Boot Loader), OS (Operating System) and Application programs to control boards through MMC based Debug board, TeraTerm and utility programs, using SD card and FLASH.

Research and Development

Confidential - San Diego, CA

Responsibilities:

• Development, implementation and prototyping of a patent granted to me in 2012 by USPTO.
• Wrote, synthesized, programmed and tested VHDL modules in Lattice ispLEVER environment and prototyped the design using ispMACH4000. Simulated modules in ModelSim PE. Designed and developed CMOS Layout in Electric environment.
• Developed ‘C’ and “Assembly” programs in MPLAB for Microchip PIC18F2525 and PIC16F883.

Senior Electrical Engineer

Confidential, San Diego, CA

Responsibilities:

• Integration and verification of Confidential MSM chips including Waverider, Aragorn and Gandalf.
• Wrote ‘C’ source code in Linux for KPSS (Krait Sub-system - ARM7/9 based controller), SPDM (System Profiling and Diagnostic Monitor), and VI (Verification and Integration) regression routines.
• Created and managed ClearCase View, Task, Activity, Elements, Checkout and checkin.
• Worked with Trace32 Debugger, CMM scripts, QSPR ( Confidential Sequence Profiling Resource), Qwebstats ( Confidential 's web-based test reporting system), ClearCase, ClearQuest, Cleartool, Citrix, RPM (Resource Power Management), Xerxes power controller and monitor system, CDP (Core Development Platform), and TCU (Temperature Controller Unit).
• Troubleshooting, debugging and analyzing PVT (Power, Voltage and Temperature) tests.
• Learned many complicated aspects of cellular phone blocks, systems and related development tools.

Senior Hardware Design Engineer

Confidential, Carlsbad, CA

Responsibilities:

• Wrote VHDL and Verilog for Xilinx Spartan6 FPGA.
• Synthesized, implemented, and programmed FPGA in ISE, and performed Floor planning, layout, PAR and verification of CMOS blocks.
• Simulated HDL in ModelSim PE and used Chipscope for debugging through Xilinx JTAG Interface.
• Designed FPGA circuits. Created and managed PCB and Schematic library components in Altium Designer IDE. Generated component footprints and schematic symbols.
• Created PCB layout, and implemented routing, part placement, back annotation, cross-probing. Generated output and Gerber files. Defined board shape, keepouts, layer stacks, high speed differential signal routing and tuning, and design rules.
• Created projects, workspace and SVN subversion version control. Managed document and design file control within embedded SVN control.
• Created components and views in 3D. Inspected and verified board and layout in 3D view.
• Debugged, verified and tested prototype board, using oscilloscope and logic Analyzer, JTAG dongle and debugger. Implemented, tested and verified Ethernet/EtherCAT IP core and automation control system through Beckhoff TwinCat hardware and software interface.

Senior FPGA Design Engineer

Confidential, Carlsbad, CA

Responsibilities:

• Developed and designed Altera Cyclone IV GXB FPGA system in Quartus II environment for RF Radio Transceiver with high speed LVDS RFCB (RF Control Bus) interface.
• Created NIOS II, code memory, FLASH, SPI, USB and I/O interfaces with Avalon bus in SOPC Builder.
• Generated new interfaces in Component Editor.
• Wrote VHDL, Test Bench and TCL scripts for simulation in ModelSim.
• Debugged the design in real time using USB-Blaster with SignalTap and EDS debugger.
• Wrote operating system, control and monitoring ‘C’ functions and routines in EDS environment for NIOS II processor and created interrupt routines in ‘C’.
• Generated HAL API BSF and FLASH programming files from sof.
• Programmed EPCS using synthesis sof and jic outputs, SFL and Quartus programmer.
• Designed and developed SLS USB using UTMI and ULPI interface.
• Designed FPGA schematic in PADS and wrote related VHDL hardware.

Senior FPGA Design Engineer

Confidential, San Diego, CA

Responsibilities:

• Developed VHDL & Verilog modules in ISE 11 for Xilinx Virtex5 FPGA.
• Created Tesbench and simulated the design using ModelSim pe 6.5, TCL (Tool Command Language) scripts. Used Vsim, Vcom and Vlog in TCL and Do commands. Created and managed libraries.
• HDK (Hardware Development Kit), I2C, Config EEPROM, PLDA BFM (Bus Functional Model), GTP PCI express x8 and MGT PCIx, Link Core, SERDES, DMA controller and FIFO, FusionXF Capability, sFPDP (serial Front Panel Data Port) Fiber channels, DDRII SDRAM, TX & RX FIFO, vm V-Metro library and modules, BSIP (Board Support Intellectual Property), PMC (Processor Mezzanine Card), XMC, ADC512 AD Converter FMC (VITA 57.1 FPGA Mezzanine Card), 1000MSPS FMC-520 DA Converter, LVDS RIO (Rocket I/O) Interface, FPE320 3U VPX FPGA Processor Mezzanine site, HSS Diff.Pairs, backplane.

Senior Hardware Engineer

Confidential, Carlsbad, CA

Responsibilities:

• Configuration, setup, test and troubleshooting of AXA-100 MicroTCA AMC modules running at 2GHz in Linux environment.
• Involved with: CorEdgeNetworks Pico-2UE chassis, CEN Power Module, SanBlaze AMC HD, PicoTCA 1US, USB FLASH memory, RS232 and mini USB I/F, Hyperlink Terminal,
• Booting Linux RedHat OS through SATA ports. Running Intel Lanconf32 program. Testing Ethernet ports. Setup and assignment of IP address to MAC, running ping, mounting USB drive in Linux.
• FPGA programming in ISE through Xilinx Parallel Interface Cable IV, and test of JSM module by Xilinx iMPACT, CorEdge BIOS debugger, Intel 82571 Gigabit Ethernet Controller, JTAG chain.

Senior Firmware Engineer

Confidential, Carlsbad, CA

Responsibilities:

• Developed firmware in IAR Embedded System IDE for AT91SAM7S256 ARM7 based controller, used in 10 GBPS optical system.
• Wrote ‘C’, Assembly and C# routines for isr, SSC, SPI, 1Wire Temp. Sensor, QSFP I/F, Flash loader, parsing, .mac, cStartup, UART, I2C Master/Slave. Used Mathlab and LabView during the development.
• Worked with SAM-BA, configuration, debugger, Jlink JTAG ICE I/F, CSPY, XLINK.
• Developed QSFP and I2C slave Verilog code in ISE for Xilinx Spartan3.

Senior HW and Firmware design Engineer

Confidential

Responsibilities:

• Designed and developed 12 layer AT92RM9200 ARM9 based controller board with 180MHz PLL, interfacing 580MHz A/D and UWB RX/TX using PCAD 2004.
• Code development, ARM9 debugging and programming using Microcross X-Tools Compiler, Linker, GNU “as” Assembler, Make, Script, Signum JTAGJET, Chameleon ICE and FLASH programmer.
• Incorporated the following modules, components and devices into the design: Xilinx Virtex IV FPGA, ARM9 controller, SDRAM, serial Asynchronous FLASH, parallel FLASH, SRAM, JPEG2000 controller, CCD timing controller and interface, Camera Link controller, Power Supply, USB I/F, RS232.
• Designed and developed VHDL modules for Virtex IV FPGA using ISE8, PACE and iMPACT programmer, Xilinx JTAG, Synplify, RTL synthesis, Timing analysis.
• Created system flowchart and block diagrams. Wrote specification documents, …