ASIC Engineer Resume San Jose, CA - Hire IT People

SUMMARY:

ASIC design engineer with experience covering architecture design, RTL coding, verification, synthesis,timing closure, scan/atpg, equivalent checking, ECO, and test pattern generation. Key strengths includeself - motivation, commitment-to-success, fast development, problem solving, and good teamworker.

TECHNICAL SKILLS:

DESIGN TOOLS: Proficient with digital design with Verilog/VHDL; Synopsys(DC, Primetime, Tetramax, VMM); Cadence(Ncverilog, Simvision, Simlink, Conformal, CDC); Mentor(Modelsim, fastscan); Verdi/Debussy; ARM, C, SystemVerilog, Shell Scripts, TCL, Perl, x86 Assembly, SPICE, logic analyzer, oscilloscope, and etc.

PROFESSIONAL EXPERIENCE:

ASIC Engineer

Confidential, San Jose, CA

Responsibilities:

Verification of MEMS product, especially on Cortex-M0, interrupt logic, and etc; built test enviroment(testbench, script, models, checkers, test cases, assertion, coverage analysis) for a microphone mixed-signal chip; tools include Verilog, NCverilog, Simvision, ARM C, ARM assembly, SystemVerilog, UVM and etc;

ASIC Engineer

Confidential, Santa Clara, CA

Responsibilities:

Verification of SSD product, especially on error-injection test for PCIe block by using Denali’s error-injection models to verify different error cases, solved rtl bugs like multi-lane skew and etc.; tools include Verilog, VCS, Debussy, Denali(Cadence) IP, AMBA/AXI and etc;

ASIC Engineer

Confidential, San Jose, CA

Responsibilities:

Verification of Memory bist and debugging logic, including test creation and simulation of butterfly and March algorithm; tools include SystemVerilog, VMM, VCS, Debussy, and etc;

ASIC Engineer

Confidential, San Jose, CA

Responsibilities:

Verification of ethernet switch products, including testbench modification, checker generation, test case generation, running regression tests, coverage analysis; testing different protocol packets(packet processing/forwarding), different layers(L2/L3/L4), different counters, internal/external memory, and etc.; the language and tools included verilog, SystemVerilog, perl, shell script language, VCS(Synopsys), VMM(Synopsys), Debussy/Verdi(Nova), and etc.

ASIC Engineer

Confidential, Sunnyvale, CA

Responsibilities:

Working on HDMI products, including synthesis, formal verification, scan/atpg, time checking, and etc. Main responsibilities were generating netlist for Synopsys to do lay-out, timing closure(pre-layout and post-layout, cross clock domain checking), equivalent checking for rtl and netlist; the language and tools were tcl, perl, shell script, verilog, ICC(Synopsys), Primetime(Synopsys), Tetramax(Synopsys), Conformal(Cadence), CDC(Cadence), and etc.

ASIC Engineer

Confidential, Santa Clara, CA

Responsibilities:

Main responsibilities include verification and test vector generation on SATA-embedded storage products; this included testbench updating, test case generation(different command/data frame, different command/link/phy layer of SATA), solved rtl bugs like sync problem, rtl/gate simulation; also ran some scan simulation(Tetramax), ran some test code(downloading ARM assembly codes to internal memory by test pins); helped lab debugging.

ASIC Engineer

Confidential, Newport Beach, CA

Responsibilities:

Working on several projects, including Ethernet MAC with phy in a multi-function processor, ADSL channel interface of a home network processor, and fax modem. It includes the entire flow from architecture design, RTL coding, verification, synthesis, primetime, scan insertion, test pattern generation, ECO, and etc; rtl design including FIFO design, sync logic design, customer bus design and etc.; generated driver and checker for block verification; rtl/gate simulation; ran synthesis, timing closure, scan/atpg, test vector generation, and ECO by using spare gates to fixed rtl problems; helped lab debugging; the languages and tools were verilog, assembly, C, tcl, shell script, DC(Synopsys), Primetime(Synopsys), Modelsim(Mentor), Fastscan(Mentor), oscilloscope etc.

ASIC Engineer

Confidential, Lake Forest, CA

Responsibilities:

Responsible for design and verification of disk controller VLSI device, particularly in the area of ECC module of the disk controller; It includes digital design, simulation, and verification. The ECC logic was implemented using Reed-Soloman code and chien algorithm; ran a lot of tests to verifify the code and algorithm; implemented register logic;

We provide IT Staff Augmentation Services!

Asic Engineer Resume

San Jose, CA

We'd love your feedback!

Resume Categories

Client Services

Job Seekers

Visa Sponsorship