ASIC design Director / ASIC design Resume Syracuse, NY - Hire IT People

SUMMARY:

I have worked on Mixed Signal IC design for years. My forte is digital design, and I am also knowledgeable in analog design. I have good personality and I am easy to communicate with. Having led several projects, I am experienced on project planning, executing on meeting scheduled milestones, and mentoring designers in the team.

PROFESSIONAL EXPERIENCE:

Confidential

ASIC design Director / ASIC design

Responsibilities:

MU2411U/G Design Lead (with 2 digital design engineer and analog team) - From IC spec to Tapeout, top level architecture define, spec discussion with other team member, design the following block (using verilog): RISC CPU, DMA, Event block, Flash Controller, Timer, RTC, GPIO, power management, and watch dog timer. This chip includes other block like USB and SPI/I2S, I2C, AES accellerator and Random number generator. There is also analog RF block in this IC. I integrate the digital top level and cowork with analog team to make sure digital-analog interface works. In FPGA verification I check some individual block. (Xilinx FPGA). After design was verified in FPGA,
MU2413 Design Lead (with 2 digital design and analog team). - I took over this project when the project lead designer left our company. At that time the project is in FPGA verification phase. This is an wireless mouse SOC. The major part of this IC is RF interface, sensor control (with state-machine SPI engine), GPIO control and power management. This is a small IC and the power is very important. I run the synopsys PrimePower to check the power of digital design. When power does not meet our target, I gate the clock with internal state generated signal. After this IC is back, we achieve our power goal and the active power of the whole mouse beat our competitor with wide margine. I also maintain the RF MAC design in this project. This MAC is compatible with nRF24LE1+ shockburst engine with automatic packet handling, auto packet transaction handling and 6 data pipe MultiCeiver, etc. Same as the MU2411, synthesis, STA, ATPG were all done by me. (2012)
New Project RF MAC design - on going, currently my family move to Dallas, so I need to travel back and forth between Dallas and HsinChu. Right now I dose not handle the whole project but design some block of the new project. This is an on going project, I might also need to take care some of the design flow like synthesis, STA, ATPG and power check, etc, this depends on the lead designer decision. (2013)

Confidential

ASIC design Director

Responsibilities:

MIPS compatible RISC CPU design maintains.
Stereo Sigma-Delta Audio CODEC test-chip digital part design.
Ethernet PHY test-chip digital part design
Integration of Audio CODEC & Ethernet PHY with DSP based SOC for VOIP application design lead
Company merged into Muchip

Confidential

IC design Senior Manager

Responsibilities:

MP3 SOC Project Lead.
Project includes memory card controller (CF, SD, SM, Nand Flash ..), Micro Controller, DSP, I2S interface, AC97 interface, USB2.0 interface and I2C interface.
Lead over 10 designers: include RTL design, MCU Firmware Design, & DSP Firmware Design.
Adopt FPGA emulation flow, capable of demo.
Project Design-For-Test includes Memory BIST, SCAN TEST, and Analog block separate test modes.
Testchip IC taped out 2003.11.18 , functional, minor hardware bug found, capable of demo.
Product IC retarget on a more advanced technology node, 2004/July.
Recruit / Train IC design engineer.

Confidential

Member Group of Technical Staff, Section Manager, Mixed Signal IC Design

Responsibilities:

All the following project are designed in VHDL
SFF small phone factor LCD timing controller + driver digital design leader.
Elected member group of technical staff -- 2000.
Digital Audio Processor with CODEC - TAS3002, TAS3004 design leader.
In charge of top-level design, Special DSP (Digital Audio Signal Processor) design, Sigma-Delta digital filter design.
These two chips have programmable 7 bands Equalizer, Loudness, Dynamic Range control and expansion and one Sigma-Delta CODEC….
LBC combo chip for central office lead designer.
In charge of A/D channel design, this is a switch capacitor filter A/D.
Noise Simulation for Switch Capacitor filter - Spice.

Confidential

IC Design Engineer

Responsibilities:

Audio Chip Design - in charge of Sample Rate Conversion, FM block
PCI Bridge Chip design - help for debug of PCI bridge chip

Confidential, Syracuse, NY

Research Assistant

Responsibilities:

Data Path Synthesizer Tool Design with C program - layout automation tool.
Opto-electronic project - tunneling diode design.

Confidential

Novell System Engineer

Responsibilities:

Novell System Installation, Administration

Confidential

Second Lieutenant

Responsibilities:

Communication Officer - in charge of multi-channel communication section.

Confidential

President of Chinese Chess Study Club

Responsibilities:

Overall manage of club include recruiting, broadcasting, communication ..

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Asic Design Director / Asic Design Resume

Syracuse, NY

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