SUMMARY:

More than 20 years in Electrical & Electronics Confidential .

TECHNICAL SKILLS:

General: Word 2010, Excel. DOORS, Ms projects, MS viso,MY SQL

Programming: Basic, Python, Perl, tcl/tk, Fortran, C/C++, Visual basic

O/S: MS - DOS 6.0, UNIX, Windows, Assembly, Red hat 6, Linux,unix

Verification: Cadence & Synopsys, VHDL,Verilog, Design Complier,UVM, System Verilog

Design: ASIC, FPGA, CPLD, RTL modeling, Constraints, Libraries, Ps/pice, TestBencher Pro

ATPG tools: Flexscan, Flextest, Quickfault, Scan insertion, DFT advisor, BIST, Scan test, Scan vectors

Simulators: Questa, NC-sim, Modelsim, Vcs, verilog XL, HS/Pice, ADS, AHDL, EDK,Quartus II

Test Systems: Genrad, Confidential 3065, 3070, Logic, spectrum &Network Analyzers, Oscilloscope, flying probe

FPGA design: Altera/Xilinx/Microsemi, V4,5,6, Kintex 7, Spartan 6, VHDL/Verilog, AHDL,HAPS board

Test Types: Regression, Automation, Manual, Acceptance, Stress, functional, integration, black &white box

Board Design: PAD flow, Allegro, OrCard, Altium,DXdesign, Schematic Capture, layouts, SI analyzes, LTpice

PROFESSIONAL EXPERIENCE:

Confidential, Sterling, VA

Lead Test eqipmentdevelopment Engineer

Responsibilities:

• Research in existing ATE System to test radar systems, Design flows, EO/IR, tests
• Full board design, PADS flow, OrCad, Schematic capture, layouts, Analog/digital, RF designs
• Test fixers, test scriptes,BSDL, EEPROM, JTAG, Assert, Testsights, TCL/TK,Perl
• Tests defined, developments, analysis, trouble shoot, debugging, qualification tests,coverages
• FPGA design, verification, validation, RTL modelings,, IP models, Matlab/Simulink
• Desgn interfaces, DDRx, USB, UART, JTAG, GPIO, signal trap, chipscope, PCIe
• NI-LabWindows,CVI, LabView, test stand, NI cards, 7820R, 5644r, 6733r,6221,Chassis
• RTOS C/C++, HW FPGA base verification platform, JTAG interface, Multi threads
• Team discussion, led teams, mentor engineers, conduct meetings, technical presentations

Confidential, Los Angles, CA

Lead ASIC/FPGA/board Engineer

Responsibilities:

• Research in existing radar systems product to develop new product, Design flows & specs.
• Design interfaces, DDR1/2/3, PHYs, PCIe,ARM, Ethernet, SATA, USB,RS232/485,DOORs
• RF Designs, Transmitters, receivers, Ethernet 1G,10G, Network, spectrum, Ethernet analyzers
• ADC, DAC, LNA,De-modulators/ modulators, Filters, OP AMPs, spliters, attenuators, Antennas
• Tests defined, developments, analysis, trouble shoot, debugging, qualification tests,coverages
• Full board design, PADS flow, OrCad, Schematic capture, layouts, Analog/digital, RF designs
• RTOS C/C++, HW FPGA base verification platform, JTAG interface, Multi threads,EO/IR
• NI-LabWindows,CVI, LabView, test stand, NI cards, 7820R, 5644r, 6733r,6221,Chassis
• Team discussion, meetings, mentor engineers, conduct meetings, technical presentations

Confidential, San Jose, CA

Principle Board Design Engineer

Responsibilities:

• C/C++ base RTOS, ARM 5,7,9,11,15, CPU architectures, I2c,SATA, AXI,APB
• Wi-FI Modem/router development based on 802.11n-MIMO technology, radios,RF design
• Design/verification engineer, acquisition, design, verification, integration of high-speed IPs
• Full board design, OrCad flow, Schematic capture, layouts, Analog/digital, RF designs
• RF Designs, Transmitters, receivers, Ethernet 1G,10G, Network, spectrum, Ethernet analyzers
• Design interfaces, DDR1/2/3 Controllers, PHYs, PCIE,ARM, Ethernet, USB, SATA, USB
• Tests defined, developments, analysis, trouble shoot, debugging, qualification tests,coverages
• Led team, Design synthesis, DFT insertions, detailed verification plan, manufacturing test plans
• Problem solving, debugging, trouble shootings, hands on experience wif lab equipments

Confidential, Sacramento, CA

Project Lead - Space Tech 

Responsibilities:

• UAM vehicle, Lead BQM163 flight program, System Design, test, support, development,EO/IR
• Multi-task & prioritize responsibilities, schedules & timelines, progress reports, Documentations
• Defined and wrote prduct, design, HW,SW,FW and certifications specifications for systems
• Full board design, Allegro flow, Schematic capture, layouts, Analog/digital, RF designs,DOORS
• RF Designs, Transmitters, receivers, Ethernet 1G,10G, Network, spectrum, Ethernet analyzers
• Tests defined, developments, analysis, trouble shoot, debugging, qualification tests,coverages
• Led team, Design synthesis, DFT insertions, detailed verification plan, manufacturing test plans
• Problem solving, debugging, trouble shootings, hands on experience wif lab equipments
• Team discussion, meetings, mentor engineers, conduct meetings, technical presentations

Confidential, Cedar Rapids, IA

Sr. Hardware Design Engineer

Responsibilities:

• ATE system deveoped for flight testings which extract and simulate test to aircraft, F-16
• Design/verification engineer, acquisition, design, verification, integration of high-speed IPs
• Defined and wrote prduct, design, HW,SW,FW and certifications specifications for systems
• ASIC/FPGA design, RTL modeling, subsystems, VHDL/Verilog,System Verilog,DOORS
• Tests defined, developments, analysis, trouble shoot, debugging, qualification tests,coverages
• Design interfaces, DDR1/2/3 Controllers, PHYs, PCIE,ARM, Ethernet, USB, SATA, USB
• RF Designs, Transmitters, receivers, Ethernet 1G,10G, Network, spectrum, Ethernet analyzers
• Problem solving, debugging, trouble shootings, hands on experience wif lab equipments
• High Speed interfaces, PCIE, XAUI,DDRx, STA, place and route, Spice simulations, ADS
• Team discussion, meetings, mentor engineers, conduct meetings, technical presentations

Confidential, Santa Clara, CA 

Lead System Engineer

Responsibilities:

• Managed, scheduled and designed an embedded system for satellite tracking & communications.
• Satellite system designs, system integrations, subsystems, system tests, system support,
• Design/verification engineer, acquisition, design, verification, integration of high-speed IPs
• Defined and wrote prduct, design, HW,SW,FW and certifications specifications for systems
• RF Designs, Transmitters, receivers, Ethernet 1G,10G, Network, spectrum, Ethernet analyzers
• Pre-sales and post-sales supports, performance reports, electrical parameters analysis
• Design interfaces, DDR1/2/3 Controllers, PHYs, PCIE,ARM, Ethernet, USB, SATA, USB
• Led team, Design synthesis, DFT insertions, detailed verification plan, manufacturing test plans
• Problem solving, debugging, trouble shootings, hands on experience wif lab equipments
• Tests defined, developments, analysis, trouble shoot, debugging, qualification tests,coverages
• Team discussion, meetings, mentor engineers, conduct meetings, technical presentations

Confidential, Campbell, CA

ASIC/FPGA & TEST application Engineer

Responsibilities:

• Custom Design & verification support for ASIC/FPGA for customers, DO 160/254
• TCL/TK scripting, test cases, Automation in scripting in TCL, DDR2, Design verification,
• Tests defined, developments, analysis, trouble shoot, debugging, qualification tests,coverages
• RF Designs, Transmitters, receivers, Ethernet 1G,10G, Network, spectrum, Ethernet analyzers
• Design/verification engineer, acquisition, design, verification, integration of high-speed IPs
• Defined and wrote prduct, design, HW,SW,FW and certifications specifications for systems
• ASIC/FPGA design, RTL modeling, subsystems, VHDL/Verilog, System Verilog,DOORS
• Pre-sales and post-sales supports, performance reports, electrical parameters analysis
• Led team, Design synthesis, DFT insertions, detailed verification plan, manufacturing tests
• Problem solving, debugging, trouble shootings, hands on experience wif lab equipments
• High Speed interfaces, PCIE, XAUI,DDRx, STA, place and route, Spice simulations, ADS
• Team discussion, meetings, mentor engineers, conduct meetings, technical presentations
• AC & DC analysis for electrical and electronics parameters, leakage& dynamic& static me
• VOH,VOL,VIH,VIL,VTH, IDDQ tests, binning, EMI/ESD, noise analysis, yield analysis