SUMMARY:

• System/ Board architecture and design covering all related HW tasks building industry’s most competitive products.
• Supporting the entire product development cycle, from concept to mass production, providing:
• Power and Thermal analysis Schematics design, (Including SI and Power Delivery Network analysis:PI) FPGA/ CPLD HDL coding/ development PCB layout (15Gbs, 32 layers blind and buried vias, products such as SBCs, SSDs Knowledge of DFT and DFM Post layout simulation (Hyperlynx, Power SI) PCB fab house qualification and supervision PCB assembly house qualification and supervision Board bring - up and debugging Product release and documentation
• Schematics design tools: Concept HDL, Orcad, Design capture, DxDesigner, and Pads logic.
• Layout design tools Allegro, PADs, PCAD and Expedition.
• Design experience with Intel processors/ subsystem, Intel’s LPC bus (Provided CPLD LPC I/O Interface in VHDL), Graphics controllers, Intel Northbridge and Southbridge chipsets.
• Design experience in SAS/SATA and PCIe SSD’s using Custom ASIC as well as PMC’s NVME controller, TLC/ MLC flash parts deploying Supercap backup power subsystem.
• Extensive design experience in dc-dc converters, Signal Integrity analysis and Power Delivery Network analysis using Cadence (Sigrity) SI and PI and also hyperlynx tools.
• Some FPGA/CPLD HDL Coding simulation and verification in VHDL (design experience with Xilinx, Altera, and Lattice FPGAs, have done multiple designs using Quartus tool).
• Familiar with Firmware coding.
• Familiar with majority of test and debug equipments.

PROFESSIONAL EXPERIENCE:

Confidential

Consultant

Responsibilities:

• Bench board design and development in DXdesigner and Xpedition qualifying company’s automotive products.

Confidential

Consultant

Responsibilities:

• Have designed and delivered some 20+ different boards since 08/2015.(Concept HDL and Allegro)
• Involved in architecture and hardware design of Microsoft HoloLens product. A HoloLens device involves the following interfaces:
• Processor core, multi rail PMIC, DDR3, WIFI, Bluetooth, multiple USB2.0, Camera (CMOS imager) MIPI CSI-2, MIPI DSI + HDMI, custom MIPI aggregate switch, Haptic and CAP touch devices, battery, pack protection, gas gauge, fast charger, Flash storage (EMMC), audio CODEC, microphones and speakers, depth camera, tracking cameras, drivers, IMU (Gyro, Accelerometer, Magnetometer). Busses deployed: PCIe, MIPI CSI/DSI,DDR3, EMMC, PCM, I2C, SPI.
• Involved in architecture and hardware design of Microsoft HoloLens peripheral products. Developed advanced technology daughter cards pluggable to HoloLens system conducting further research.
• Designed and developed a flying spot detection system, employing high speed Photo Diodes, high BW low noise OPAMPs, DACs, a USB3.0 controller and an Artix-7 FPGA. This project involved the design of 3 different cards. Did the PCB layout of one of the cards in allegro.

Confidential

Responsibilities:

• Designed and developed an embedded system that includes the following blocks:
• Quad 64-bit ARM cores, PMICs chipsets+ additional buck-boosts and LDOs, LPDDR3 memory interface, audio codec, PCIe, USB3.0, Battery fast charger+ Battery, WIFI, Bluetooth, haptics, capacitive touch, Gyro, Accelerometer, Magnetometer and implementation of several CSI-2 image sensors.

Confidential

Consultant

Responsibilities:

• Designed the hardware and delivered a flawless first FAB FPGA based 24 DIMM DDR3 data storage card.
• Designed the hardware and delivered a flawless first FAB 200Amps power module subsystem.
• Helped firmware team defining and mapping the tasks of local management controller.
• Deployed board bring-up and hardware system post qualification.

Confidential

Consultant

Responsibilities:

• Designed and developed ASR9K family Starscream Fabric card using Cisco’s latest Fabric switch ASIC. This card plugs into Starscream chassis, supporting 10 line cards, 2 ports per line card, with an aggregate traffic of 2.4Tbs. The chassis supports 2 x Router processor cards, 7 Fabric cards, and 10 linecards.
• Covered the schematics of all sections of the design, supported the layout team, defined the stack-up and provided the guidelines to route 15Gbs on Megatron6G core material.
• Other activities included board debug and bring-up of other Cisco router cards, hardware functional spec and documentation for EDVT and other qualification testing tasks.

Confidential

Consultant

Responsibilities:

• Provided a solution to increase storage capacity on a single channel.
• Created an algorithm that analyzes the effective charge of any type of super cap under a certain temperature and charge voltage after X amount of years.
• Created product design guideline document that covered product compliance with EMC, HP and IBM requirements.
• Designed and architected Industry’s Best in Class 4TB PCIe Gen3 SSD card with over 1GB/s sequential write speed.
• Architected, designed and debugged the complete hardware of a 4TB PCIe G3 and SAS SSDs using Company’s 18 channel storage controller and IDT’s NVMe controller devices. All products supported temporary backup power/ charger subsystem.
• Architected, designed and debugged the complete hardware of Company’s 1.8 “(credit card size) uSAS SSD Product. Form factor is 54mm x 71mm x 5mm supporting supercap backup power/ charger subsystem. This product is being shipped to IBM by mass volume.
• Proposed a new solution and redesigned company’s 1TB SATA 2.5” SSD product.

Confidential

Consultant

Responsibilities:

• Designed and developed a low cost telepresence product based on TI's OMAP4460 processor, and TWL6030 PMIC.
• Designed and developed a HDMI repeater module, providing pass-through mode and supporting 4 HDMI ports.
• Cost reduction of Consumer first generation Tele-presence product
• Re-designed the power distribution system of a UMi product reducing cost >30%.
• Re-designed the PCB stack-up, which yielded a reduction in layers from 18 to 12 layers, supervised the layout.
• Provided post layout simulation and xtalk analysis. (Optimized termination values)
• Solved the EMI issue of older system.

Confidential

Consultant

Responsibilities:

• FPGA code development and board debug/ bring-up.
• Developed FPGA code that provided SSBI interface, plus frequency counting and some miscellaneous LABVIEW tasks.
• Provided debug and board bring-up of an FPGA bench mother board to support PMIC cards.
• Development of multi socket ATE boards for test, characterization and production of all Qualcomm chipsets
• Research, characterization and simulation of RF (3GHz) traces on Nelco 4000-N13, 30 layer load boards implementing 50 ohm Vias and custom connector models.
• Designed and developed both schematics and PCB layout for Nighthawk 1X characterization ATE board.
• Designed and developed the production ATE loadboard for Nighthawk 4X.
• Designed and developed the ATE loadboard to characterize QTR8600 chipset.
• Designed and developed the ATE loadboard plus ST card to verify the mechanics of the new POP Halcyon socket.

Confidential

Consultant

Responsibilities:

• Developed the VHDL code for an ACTEL Fusion FPGA used on Aries-1902 product (3U version of Aries 1952).
• The code covers Reset logic, IPMI controller, LPC bus with serial IRQ support, 2 UARTs, watchdog timer, 8 GPIO's with level/edge trigger interrupt capabilities, plus other miscellaneous logic.
• Developed the VHDL code for an Altera CPLD used on ARIES-1952 6U VPX Intel Core2 Penryn board.
• The code covers reset logic for system and peripheral controller modes, LPC interface with serial IRQ support, 8 GPIO's with level/edge trigger interrupt capability, write protect logic plus other miscellaneous logic.
• Designed and developed an Intel Core2 DUO base Single Board Computer with VME interface. The product incorporated 4 GB of DDR2 400, Intel Northbridge/Southbridge chipsets, (DxDesigner and Expedition). This SBC supported 2 PCIx 133MHz-PMC sites, ATI PCIe x8 Video interface, PCIx-Dual SCSI U320 interface, Dual PCIe to GIGe Ethernet, 2 PCIe-PCIx 133MHz bridges and a 64 bit VME to PCIx bridge. Devices sitting on South Bridge LPC interface were: BIOS Flash, CPLD, Super I/O chipset, and an Intel Security TPM controller.
• Used a lattice power sequencer device to manage the complex sequencing mechanism of the 16 power rails (dc-dc's and LDO's).
• Provided the following documents:
• Board hardware functional document.
• Hardware design block diagram.
• Board Power Consumption spread sheet.
• Thermal analysis spread sheet.
• Clock distribution diagram.
• Reset distribution diagram.
• Interrupt routings diagram.
• JTAG chain diagram.
• SM bus chain diagram.
• Board Power Sequencing flow chart.
• CPLD VHDL coding: LPC Interface, Reset logic, PCIx Clock Detection and Control.
• Provided the following SI tasks:
• Board stack up (20 layers) and trace requirement to meet 75ohms RGB, 100 ohms differential, 90 ohms USB and 125ohms differential SCSI. Signal Integrity post layout simulation using Hyperlynx 7.7, provided the adjustments required and a comprehensive report on DDR2 interface and FSB interface (quad pumped data at 800MHz). Cross talk analysis for the entire board. Board bringup and Debug
• Designed and documented a 128GB USB Flash storage PMC/ XMC Card, (DxDesigner, Expedition).
• Provided post layout simulation and board stack-up using HyperLynx tool.
• Supervised PCB layout work and supported parts procurement team with early stage BOM and other documentations.
• Provided product requirement and detailed design documentation.
• The board architecture entails PCI to PCI, PCIE to PCI bridges, 2 PCI-USB host controllers, and 8 USB-NAND flash controllers.
• It supports both air-cooled and conduction cooled up to L200 level.
• Development duration from concept to 100% working prototype was 11 weeks.

Confidential

Principal Hardware Engineer

Responsibilities:

• Designed and developed a single board computer system using Altera's QuartusII software and SOPC builder and put together a system on a chip that included a Nios 32 bit CPU core, SDRAM controller, Strata flash, MAC, UART and several other interfaces (in VHDL).
• Provided the VHDL interface to an Arcnet chip (for back plane communication) running at a different clock speed.
• Provided the module in charge of environmental variation. Used Altera's NIOS application software, wrote a C++ application program downloadable via JTAG (Emulation software) to debug and verify the HDL design on the actual board.
• Provided DVT document template, being used as reference DVT document.
• Supervised the schematic capture and board layout design of 3 new products.
• Assisted in debug and board bring-up of multiple digital control boards.

Confidential

Senior hardware Engineer

Responsibilities:

• Designed a low cost SAS/ SATA 2U midplane (Used Mentor Graphic's Design capture tool), interfacing to a PCI riser card via PCI Express connector, carrying 24 pair SAS/SATA Drive signals plus controls over I2C bus.Used a Lattice ISPMACH4256V CPLD, supporting I2C slave on one end, and Confidential 's,Drive Power MOSFETs control, Drive Status registers. Implemented a low cost(below $7) 12V to 3.3V @ 20A DC-DC converter (TI's TPS40100), and a -12V @ 0.2A (TI's MC34063A).
• Designed and developed the Schematics (Orcad) and Board Layout (P-CAD) for a 4.25GHz Fiber Channel Host adaptor board 4 layer FR4. The board implemented 4x4 GHz SFP's, power distribution and low pass filters, 100 ohm impedance controlled 4.25GHz fiber channel routing from SFP's to mezzanine connector.
• Modified the schematics and board layout lowering the cost of an existing product, resulting over $1M / year savings.
• Designed and developed the Schematics (Orcad) and Board Layout (P-CAD) for different SATA MUX dongles sitting behind SATA drives.
• Provided the Root Cause Failure analysis for 2.125 GHz Fiber Channel product.
• Provided Jitter measurement analysis using JIT-3 analysis tool running on TDS7404 TEK Oscope/ Saved over $1 million cost on company's main product by changing the design and switching to a significantly lower cost CPLD. Wrote the HDL coding, re-did the schematics(Orcad) and layout of the board (PCAD).

Confidential

Project Lead Engineer

Responsibilities:

• Provided the board design and development alsoHDL coding of a high speed FPGA based data acquisition system.
• Provided the HDL coding (AHDL) on an ACEX1K30 FPGA, the code supports:
• 2 synchronous clocks; one running at 200MHz and the other controlled by the onboard Controller.
• A Synchronous 32-bit SRAM interface running at 200MHz
• An optimized algorithm that provides an efficient use of the external memory.
• An 8-bit synchronous bus interface supporting the on board USB controller.
• A mini-UART interface for debugging.
• Access to the internal EAB's, via the 8-bit interface.
• A handshake interface used for Master/ Slave synchronization.
• Performed timing simulation and floor plan optimization.
• Provided the Schematics design and Bill of Material. (ORCAD)
• Provided the Pre and Post layout signal integrity simulation (Hyperlynx tool),and optimized the Provided the PCB layout design (PADS)

Confidential

Project Lead Engineer

Responsibilities:

• Provided the detailed Power Supply design and its thermal analysis.
• Provided the cost to build in high volume production.
• Provided the hardware functional Specification.
• Provided the detailed schematic design with Orcad tool (Cadence).
• Provided the PCB layout design with PADS tool.
• Provided Post Layout Signal Integrity Simulation.
• Provided the post assembly board initialization and bring-up
• Provided DVT documentation.

Confidential

Project Lead

Responsibilities:

• Provided the Hardware Functional Specification
• Provided Schematics design (Orcad)
• Provided HDL Coding / simulation of CPLD (EPM3128ATC144-10)
• Provided Pre/ Post Layout Signal Integrity Simulation using IBIS models
• (Hyperlynx)
• Provided PCB layout Guidelines for a 12 Layer Controlled Impedance Board.
• Provided PCB layout Part Placement (Visio =>PADs)
• Interacted with the PCB designer throughout the layout process
• Provided JTAG Boundary Scan, PCB Interconnect Testing (Corelis)
• Wrote the ROMInit code that initialized and brought up the hardware (VXWORKS)

Confidential

Project Lead

Responsibilities:

• Provided the Hardware Functional Specification
• Provided Schematics design (Orcad)
• Provided the HDL Coding / simulation of board control CPLD (EPM3128ATC144-10)
• Provided Pre/ Post Layout Signal Integrity Simulation using IBIS models(Hyperlynx)
• Provided PCB layout Guidelines for a 15 Layer Controlled Impedance Board.
• Worked with the PCB designer in parts placing and Layout
• Provided JTAG Boundary Scan, PCB Interconnect Testing (Corelis)
• Wrote the ROMInit code that initialized and brought up the hardware (VXWORKS)

Confidential

Project Lead

Responsibilities:

• Defined the Hardware Functional Specification
• Schematics design (Orcad)
• Provided HDL coding of the CPLD (AHDL, Verilog)
• Defined layout guidelines for the 2 Gb/s Fiber Channel interface, and 2.0Gb/s Serdes interface plus 133MHz system bus (memory bus and MIPs synchronous bus).
• Defined Hardware DVT Plan, including Signal Integrity and Eye Diagram
• Verification on all high-speed serial lines.
• Supported Firmware and Design assurance team