SUMMARY:

A senior engineer with a master’s degree in Electrical Engineering and extensive experience in the semiconductor industry. Experienced in cache memory design and test, chip clocking and clock methodology, software development, front end verification, Confidential Microprocessor architecture, CPU Micro Architecture, product development, post Si validation, and testing digital circuit devices. Results oriented individual contributor and a motivated team player who is committed to learning and generating new technologies and methodologies.

SOFTWARE, TEST AND DESIGN TOOL KNOWLEDGE:

Operating Systems: UNIX, MS - DOS, Windows

Computer languages: C++ (OOP), C, Perl, Assembly, Verilog, (SV) System Verilog

Development Tools: UVM, Solaris with UPS Debug environment

Tester platforms: Advantest T2000, Credence S9K ASAP, Teradyne J973 IG900, IMS

Circuit Design applications: Cadence Virtuoso Schematic Editor, Synopsis PATHMILL, SPIDER, MAGMA

Circuit Simulation: Hspice (and CSCOPE), Presto( lynx ), PSPICE, NOVA

Layout Tools: Cadence Virtuoso VXL, Genesys, Laker, Calibre

BE Verification Tools: Nanosim, NoiseSim, Verplex/Conformal, GARNET

FE simulation/tools: Spyglass, nWave, Questasim, Lint, Formal, UVM, DCT, Rambo, Gpro

EXPERIENCE:

Staff Design Engineer

Confidential, Chandler, Arizona

Responsibilities:

• Contributing to the L1 memory team and driving the efforts as the verification lead on hardware security development for the next generation M-class processor.
• Contributor on the L1 memory verification team for the next generation Confidential V8.1M microprocessor.
• Completed the detailed investigations for three main sub-units of the memory system: DCU, STB, and BIU, created time estimates for their verification tasks, and authored the TB sub-unit checker specifications for each.
• As a member of the memory verification team, supported the L1 TB unit team by developing various test bench components of the memory unit in a UVM environment.
• Integrated the L1 memory-unit into top level verification environment and enabled top level testing of it.
• Integrated the L1 core memory-unit into the Multi Processor testbench environment. Coded all the functionality for funneling cpu events into the MP TB, and enabled all related unit level checkers as well as MP memory coherency and order checkers. Assumed ownership of the MP side checkers, and scoreboards.
• Debugged, root caused and filed many RTL bugs.
• Made numerous enhancements and bug fixes to the L1 TB, and MP TB. Key accomplishments:
• Drove the effort and development work to enable verification of the multi-cluster/multi-unit test bench for an A-class core.
• This was to ensure the robustness of Confidential ’s memory coherency and ordering in a multi cluster/core setting.
• Worked with stimulus team, and L3 memory team to coordinate this effort.
• End result was the delivery of a robust coherency testing and verification platform that discovered numerous bugs ranging from core memory RTL, interconnects, and the L3 memory unit.
• Supported the L1 Unit level TB verification team by developing several scoreboards, checkers, BFM’s.
• Debugged and resolved numerous TB bugs. Along the way root caused and filed several memory units RTL bugs.
• This effort ensured that the unit level L1 verification team met all their deadlines, and delivered a quality TB with robust RTL verification quality.

Staff Component Design Engineer

Confidential, Chandler, Arizona

Responsibilities:

• Developed the behavioral model in UVM environment for the major and critical schedule RTL unit using OOP in System Verilog. Coded all the checkers required by the RTL designer. Suggested and coded several more checkers.
• Also developed the Front End Cluster’s Uop agent in the same test environment.
• As part of helping the memory team, developed the behavioral model in UVM environment for the Snoop protocol using OOP in System Verilog. This BFM checks all cache levels and cache lines for proper coherency status, generates the proper snoop response and compares with actual.
• Wrote and reviewed the DIS unit MAS and the DIS DOA test plan. Completed the synthesis feasibility for the DIS unit. Completed the RTL coding for the DIS unit. Added assertions/assumptions to DIS RTL code. Completed baseline quality checks (Spyglass/Autocheck/Formal/DCT). Completed and reviewed DIS Test Plan. Debugged DIS unit and helped team in debugging cluster. Supported the verification engineers to develop unit TB.
• Drives the validation effort for the randomly generated test suites across multiple platforms and flavors. Executed billions of random instruction tests on a weekly basis and led the team in bug filings 3 years in a row. Accurately root caused bugs to functional unit, and when time permitted root caused to line of code.
• Developed several new random templates and enhanced most inherited ones. These included developing full trust-zone enabled templates, developing template for VFP (floating point coprocessor) instructions for thumb mode, custom building templates for specific bug signatures, enabling endianess mode testing, and added numerous macros and functions requested by RTL designers and architects.

Senior Circuit Design Engineer

Confidential, Chandler, Arizona

Responsibilities:

• Reviewed and audited the clock quality on RLS and custom functional blocks. That included ensuring clean slopes, insertion delay and pulse width.
• Worked with functional block owners to resolve any issues.
• Co-developed, and implemented the top level clock tree synthesis validation plans for the TTM product. Validation included simulation of critical clock routes extracted through MAGMA tool, and clock devices used by the synthesis tool.
• Ensured that all design constraints were implemented and that all design targets were achieved.
• Key contributor on Manzano Custom Circuit Design group. Assumed ownership of the L2 State and Tag caches over 3 process steppings and L2 data cache on one stepping. Main responsibilities were to ensure a robust design of these blocks through race checks, statistical circuit analysis to determine minimum SenseAmp vdiff, rectifying bugs discovered by Si debug team, maintained a clean timing model by fixing several speed paths, and performed all design verification processes.
• Authored and Generated the “Cache Race Check Methodoloogy and Training” document. Presented this document to circuit design teams and provided training for team members.
• Utilized the race check methodology to enable the team to cover the L2 cache units (L2S/T).
• Performed race check validation and resolved all race problems; this included the L2 data cache for the 1213E0 process.
• Thoroughly analyzed the results of edits during the race check validation, ensuring they did not create other problems within the design.

Senior CAD Engineer (Test Software Development)

Confidential, Chandler, Arizona

Responsibilities:

• Dynamic test template design and development: Developed ADC test template functional specifications supporting PDE requirements.
• Provided design and review of supplier CMT test platform critical to mixed/signal analog module development.
• Reviewed DSRC/DMEM, Standard Interface, Pattern Management, Waveform Object Class, Pattern Sequence, and OTPL.
• Provided design and review of supplier CMT test platform critical to mixed/signal analog module development.
• Reviewed DSRC/DMEM, Standard Interface, Pattern Management, Waveform Object Class, Pattern Sequence, and OTPL.
• Drove requirements gathering, architected, implemented (using C++ OOP) and validated embedded array test methodologies as part of CorTeX test class library for microprocessor testing. These sophisticated algoritms were developed to meet requirements from across Confidential product groups, and were capable to handle multiple DUTs and test heads in parallel.
• Responsible for developing standardized test methods on various tester platforms to support Intel’s microprocessor product teams.
• Specific responsibilities included ownership, development and deployment of all cache testing related templates, code, and array test algorithms and customer support. Prized accomplishments:
• Designed, architected and developed test class code for Scoreboard, Redundancy-Repair, Raster, and Low Yield Analysis (LYA) test templates.
• Created robust and sophisticated algorithms to meet the complex requirements from across all Confidential product teams.Provided off-site training classes for product engineering teams.
• In addition to the embedded array test methods, ownership included ScanFI, Shmoo, SampleRate, Datalog, Thermal Sense, and over 50% of the common code capabilities in iPackage test template library.
• Provided exceptional technical support to the Prescott SORT and CLASS teams as well to other PE groups. Assumed the ST2 technical team leader position on an interim basis. Supported ST2 team members in several key technical issues such as iP frequency search and iP icc pat trig template and code problems. Resolved and root caused most 2X parallel efficiency issues such as power downs, DC template parallel test times as a member of the SORT 2X task force.
• Developed from scratch the full kitchen-sink pattern set for the NPTest’s IX and DeFT test platforms. This pattern set was developed for standard and non-standard arrays and was used as the generic pattern library for all products.

Confidential

Processor Senior Product Engineer

Confidential, Hillsboro, Oregon

Responsibilities:

• Assumed ownership of clock compensation test methodology, completed development and added requested fuse override capability and phase detector offset application.
• Detected an error in the original offset DE supplied algorithm, and proved to DE using real data examples.
• The offset application was required for clock compensation to work at all which was later proven on Silicon. Debugged the clock compensation algorithm with DE on the IMS platform.
• Key contributor to enable the algorithm to work on 1st Si within 24 hours of first units.
• Developed the test methodology for the Willamette processor’s thermal sensor circuit. The test methodology included a binary search for the sensor’s trim value, stuck at fault and noise test, offset application, and catastrophic tripping tests.
• Published and presented this test methodology to Test Program working group. Worked with design engineers to answer their circuit concerns.
• Generated ECO to improve circuit design for testing.
• Generated user code to be implemented in Willamette test program and performed 1st Silicon debug.
• Created the test capability for the Willamette test chip thermal sensor circuit on S9K IX platform. Debugged the test patterns, and validated the design of the circuit through dc and functional testing. Worked with DE team to convey and resolve problematic issues.
• Developed the timing and levels blocks, opens/shorts, Vcc continuity, vix/vox for the Willamette test chip on the J973 ST platform.
• Developed and owned timings for Willamette processor J973 ST test program. Integrated a couple of Willamette test program revisions.
• Validated the NVRAM, power sequencing, and Job Init aspects in the latest release of the Teradyne IG900 software.
• Also validated the High Current Power Supply as to meet Willamette processor power requirements.

Celeron Processor Product Engineer

Confidential, Hillsboro, Oregon

Responsibilities:

• Main assignments were FA/FI and system test time reduction for Celeron processor factory support.
• Responsibilities also included supporting Pentium II design team in device characterization on S9K VLSI tester, maintaining and updating all Pentium II S9K Test Programs, helping test pattern team to debug S9K patterns for different processor stepping, and supporting SECC PE team in FA/FI using the S9K tester. Key accomplishments:
• Developed failure analysis failure isolation procedure for Celeron processor. Performed the above task on customer returned units and trained overseas factory PE’s. Successfully transferred FA/FI procedure documents and tasks to factory.
• Mini characterization of Celeron processor through S9K shmoo data collection across different test corners.
• Test data collection and analysis on factory defects (scoreboarding) to use in Test Time Reduction TTR data analysis.
• This task was aimed at reducing Systest test time for the Celeron processor by eliminating 0 DPM, and redundant tests through statistical analysis of the scoreboarding data. Gained experience on Systest and PPV station.
• Setup of ITP565 debug station HW/SW for Celeron processor.
• Created fuse programming scripts for engineering and factory use.
• Created an interactive C++ program to generate the fuse code as the user wishes to program his SECC product.
• Trained PE’s from different Confidential sites on ITP565 setup, fuse methodology, and fuse programming.

Product Engineer

Confidential, Hillsboro, Oregon

Responsibilities:

• Used the core plga test program blocks to develop the S9K Test Programs for the three SECC products: DS1P, DS2P, and MPII. This task included the development of the processors signals Pindef, Levels Blocks, Timing Blocks, Opens/Shorts tests, Vcc and Vcc L2 continuity tests, DV Functional tests, Test Flow, User Functions manipulation, and DV scripts for data collection. Debugged the WCIO pattern suite, as well as the Test Programs. Transferred Test Programs and test patterns to different sites.
• Developed the S9K TIU’s for DS1P and DS2P products. This effort included providing the specifications, requirements, and support to ITTO, the TIU designer. Interacted with the DS1P and DS2P design teams to provide the above. Developed the TIU validation Test Program for the different products and supported team members on TIU validation. Discovered signal integrity problems and their sources in TIUs. Proposed and successfully implemented plans to overcome the signal integrity issues in the TIUs.
• Supported senior engineer in data analysis, by providing technical information on tester hardware, test program, and test methodology. Performed shmoos and other tests to verify the nature of marginal parameters found through data analysis.