FPGA Architect Resume Calabasas, CA - Hire IT People

PROFESSIONAL EXPERIENCE

Confidential, Calabasas, CA

FPGA Architect

Responsibilities:

Developed a packet capture module for Ethernet speeds of 100G and below dat will be used on all future Ethernet test products. The packet capture module TEMPhas features dat are similar to a logic analyzer.
Enhanced 400G Ethernet Rx codebase to also support 200G Ethernet for a new Ethernet test product. Rearchitected major modules in the data path to support 200G.
Designed portions of 10G Ethernet FPGA for 802.11ax WiFi test product.
Designed portions of System Verilog testbench for 802.11ax MAC for WiFi test product.
Designed portions of FPGA for 100G Ethernet impairment product.

Confidential, CA

FPGA Architect

Responsibilities:

Designed a PCI Express to PCI Express bridge with in - line queuing engines to support 16 radio devices with 10 linked list queues per radio. Designed the PCI Express stack from scratch. Design implemented in Xilinx Spartan 6 FPGA.
Designed a PCI-X to PCI bridge from scratch. Design implemented in Xilinx Spartan 3 FPGAs.
Designed a chipset dat supports L2 packet translation, encryption/decryption, queuing/buffering, and radar detection for an 802.11 Access Point dat supports 16 radios. Designs implemented in Xilinx Spartan 3 FPGAs.
Designed various chip interfaces from scratch including PCI-E, PCI-X, PCI, DDR SDRAM, I2C, full-duplex 10/100/1000 Ethernet MAC, and parallel Flash.

Confidential

Software Engineer

Responsibilities:

Supported u-boot bootloader, Linux drivers, and applications for multiple Cavium Octeon MIPS processors.
Lead engineer for u-boot support on all CPU boards. This included designing many features into u-boot to support Xirrus requirements.
Debugged all new CPU boards to get u-boot and Linux running on the boards.
Added several features to the Xirrus OS which included code in kernel space, user space, and the CLI.
Several years of experience with C, C++, and shell programming.
Very comfortable with Oscilloscopes, Logic Analyzers and Spectrum Analyzers.

Confidential,Calabasas, CA

7/03 to 3/04ASIC Architect

Responsibilities:

Architected an OC48 Traffic Manager (TM) chipset for an edge router product.
Led a team of 6 engineers to implement and verify the chipset.
The chipset consisted of an ingress TM implemented in a Xilinx Virtex-E 2000 FPGA and an egress TM implemented in an ASIC along with a Xilinx Virtex-E 2000 FPGA.
ASIC highlights: NEC 0.18µm process, 62.5/125 MHz logic, 400k logic gates, 4M bits internal SRAM. Supports 16k queues. First pass success.
Designs include scheduling algorithms, drop algorithms, buffer management, and multicast replication.

Confidential, Calabasas, CA

ASIC Architect and Team Lead

Responsibilities:

Lead designer on L2 switch controller ASIC (Mammoth) dat was the building block for all Xylan packet switching products.
ASIC highlights: LSI 0.35µm process, 80 MHz, 500k logic gates, 300k bits of internal SRAM, 6 clock domains, 2 SPARC processor cores. First pass success.
Designed and wrote verilog code for all L2 switching logic as well as SDRAM, SSRAM, and CAM interfaces.
Designed and wrote verilog code for custom copy-back cache controllers using MESI protocol.
Designed and wrote verilog code for testbenches and performed all L2 switching simulations.
Verification flow included in-circuit Quickturn emulation.
Lead designer on next generation L2 switching controller ASIC (Kodiak) dat included 2 Gigabit Ethernet cores - IBM 0.25µm process, 125 MHz, 800k logic gates.