Web Designer Resume

TECHNICAL SKILLS:

Languages: C, HDL (Verilog, VHDL), SystemVerilog, X86 Assembly, Python.

Cadence Tools: Composer Schematic, Virtuoso, EDI Encounter, ICC2.

Synopsys Tools: Design Vision, Primetime, Waveview, DVE, Library Compiler, Liberty NCX, Siliconsmart, Tetramax.

Simulation Packages: Hspice, Xilinx ISE, MATLAB, Cplex, Gem5, EAGLE, TINA, Multisim, EDA, Pspice.

Others: Linux Shell scripting, semiconductor design, pre - silicon verification, CMOS Design, Mentor Graphics, Memory Testing, verification, altera, software design, Confidential architecture, BIST, scan chains, JTAG, DRC, LVS, XOR, SoC architecture/design , Low Power Design, SPI/I2C protocols, Test Generation, Design validation .

Operating Systems: Windows, Unix, MS Office suite, Linux.

Related coursework: Testing and Testable Design, Application Specific Integrated Circuit Design( Confidential ), VLSI Design, Hardware Description Language, Microprocessor, Switching Theory and Logic Design, Advanced Digital logic, RF and microwave circuits, Computer Architecture, Wireless Sensor Networks, Optical Communication Systems, Active Semiconductor Systems.

PROFESSIONAL EXPERIENCE:

Web Designer

Confidential

Tools: Xilinx ISE, Cadence Virtuoso Layout editor, Silicon Smart ACE, Design Vision, Hspice, Waveview, Encounter tool, Primetime.

Responsibilities:

Designed RTL and implemented an Arithmetic Logic Unit which performs N bit arithmetic operations using Xilinx ISE and Verilog.
Designed standard library cells using 130nm technology in Cadence Virtuoso Layout editor for standard gates.
Performed DRC and LVS checks.
Functionality check of the designed cells using Hspice, waveview.
Library characterization using Silicon Smart.
Mapped netlist generated from the Verilog code of the designed ALU using design vision.
Automatic placement and routing of the ALU using Encounter tool.
STA: Performance (worst case delay, slack) of the design estimated using Primetime.

Confidential

Digital Audio Processor

Tools: Synopsys Design Vision, Xilinx, ModelSim, Synopsys IC Compiler.

Responsibilities:

Designed a Low Power Confidential - Confidential chip to implement an FIR filter used in hearing aid devices.
Used C programming and behavioral Verilog to build the RTL of the Two Channel Confidential .
The architecture design of the Confidential was then done and codes using Verilog.
Synthesized the design using Design Vision Synopsys tool and generated the netlist.
The netlist was then used to generate the layout and floor plans(placement and routing) using IC Compiler Synopsys tool.
The power, static timing, clock tree synthesis and area analysis of the Confidential was also done to find out if design goals were met.

Web Designer

Confidential

Responsibilities:

Asynchronous Circuit Design & Implementation: designed a Pump Controller using asynchronous and synchronous, Mealy and Moore FSM's.
Performed Confidential for combinational, sequential circuits and designed characteristics before and after scan insertion (area report, timing report, delay report) in TETRAMAX.
Designed Built in Self-test for 8-bit ripple carry adder and an 8-bit comparator by adding 8-bit pseudorandom generator (16-bit External XOR LFSR) and 4-bit signature compactor (4-bit MISR), using Verilog modeling and observed the fault coverage before and after BIST insertion.
Reverse engineered a 32bit ARM processor with an 8-bit data bus. A Verilog code was written to perform the instruction decoding, FSM for the Controller, and the ALU for the computation.

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