Intern, Resume,

SUMMARY

1 year of experience as Confidential Design & Verification.
Undergoing training Confidential Verification.
Expert in Verilog and System Verilog programming languages.
Hands on experience in writing RTL design codes.
Strong fundamentals in Digital Electronics.
Good noledge of Design of Digital IPs.
Expert in debugging and Simulation Issues.
Good Exposure to Simulation wif Questasim, Modelsim, cadence, Xilinx ISE and VCS tool.
Knowledge in Code Coverage & Functional Coverage.
Excellent communication, debugging skills and a strong team player.
Good noledge of CMOS and Embedded System.
Knowledge of ANALOG,STA, layout design & DRC, LVS.

TECHNICAL SKILLS

Verilog, System Verilog, UVM, VHDL, C, C++, Microcontroller programming.

Protocols: AMBA - AHB.

HDL Simulation Tools: Modelsim, Questasim, Xilinx, Cadence

Coverage Tools: Functional coverage, code coverage.

Synthesis Tools: Xilinx ISE.

Operation Systems: Linux, WINDOWS7, xp/2000

PROFESSIONAL EXPERIENCE

Intern

Confidential

Responsibilities:

Design of BCH & LDPC encoder IPs as per teh DVB-T2 Standard.
Cross checking results wif reference code.
FPGA implementation.
Developing teh Dual Port RAM.
Developing teh test scenarios.
Developing teh verification components using system Verilog.
Developing AMBA-AHB Protocol verification environment.
Understanding teh AHB Protocol.
Developing teh master & slave BFMs.
Developing teh test scenarios,
Developing teh verification components using system Verilog.
Qualified in GATE 2012.
Attended workshop on “ASIC Design using Open source EDA”, Confidential .
coordinator in samveeshana2012 (S.G.B.me.T,Belgaum)
Attended National conference on Confidential and Presented Paper in Confidential, Confidential .