Component design engineer Resume

SUMMARY:

Worked in CPU and GPU team in Confidential on RTL Design, RTL Verification and System Validation (Emulation & Post silicon) as Individual Contributor and team lead.
Experience in RTL Design, Verification and Debugging using System Verilog, Verilog, VHDL, OVM and UVM.
Expert in both Hardware and Software Engineering.
Expert in hardware emulation systems (Veloce, ZeBu etc.)
Extensive experience in System Validation & Debugging issues for CPU & GPU.
5 years of working experience of tools such as logic analyzers, SATA, USB, and PCIe bus analyzers.
5 years of working experience of tools such as schematics capture, PLD, PCB layout, signal integrity.
15 years of experience in simulation.
Extensive experience with unix/linux and scripts (shell, ruby, tcl, perl etc.)
Expert in SOC System Validation
Extensive experience on C++ and Graphics Technologies like 3D.
Experience in Graphics Pipelining, Power Delivery Network(PDN) and Wireless Power Charger

PROFILE:

COMPUTER EXPERTISE:

Operating Systems: UNIX and Windows.

Hardware Description Languages: VHDL, AHDL, IHDL, Verilog

Computer Languages: PROTO, PERL, E, Assembler Language, C++, C, FORTRAN 77, Windows Programming, System Verilog, UVM/OVM.

CAD Tools & Packages: Altera, Max+Plus II, Xilinx, Magic, Mentor, SPICE3, PSPice, IRSIM, MATLAB, AutoCAD, MS - Office.

WORK EXPERIENCE:

Confidential

Component design engineer

Responsibilities:

Developed a PERL script to get automated capture of failures from emulation.
Debugged failures with waveform and looking at the source code.
Graphics Technology Interface(GTI):
Lead GTI Pre-silicon Validation for few projects. Built the GTI Validation platform from scratch in the team. Developed test-plan and tests and found HW bugs from the new tests. Did planning on assertion based validation and debugged 3D failures.
Worked on Concurrency testing for 3D+ units. Developed new concurrency tests to in corporate full-pipe 3D tests including Media/Display components.

Confidential

Graphics Processing Unit (GPU) Engineer

Responsibilities:

Lead Media(Video Encode/Decode Engine) Pre-silicon Validation for the team. Made necessary planning for different stages of Media Validation & met all milestones.
Owned the Media decoder validation for the team and took stretch goal to meet all milestones.
Wrote tests, debugged and validated the decoder component during different stages of pre-silicon validation.
Helped other media components to meet the project milestone.
Worked as Media Performance Testing coordinator and ran the Performancecoordination meeting with all internal and external stakeholders.
Coded DPI tracker for performance debug for all media components.
Collected and debugged performance data for decoder component from Pre-silicon.

Confidential

Graphics Processing Unit (GPU) Engineer

Responsibilities:

Designed two units for four projects with Verilog/System Verilog.
Designed the units in (Field-Programmable Gate Array) FPGA.
One unit was designed from scratch. It has frequency conversion and also process different messages coming to Sampler. It also interfaces with four other units. Did unit level validation of the unit. Worked on timing analysis and resolved different violations.
The other unit computes Level of Details, does some sequencing, normalizes offsets, deals with cube mapping etc. Did unit level validation of the unit. Worked on timing analysis and resolved different violations.
Worked on SPECMAN model for the three arbitrar units.
Helped team with PROTO advice including providing . Developed PROTOs for stress testing and debug failures.

Confidential

Component design engineer

Responsibilities:

Contributed towards Cluster Testing Environment and template development and enhancement for cluster level testing with E language.
Developed new Test-plan & proto and also enhanced & maintained existing protos with continuous RTL changes.
Wrote focus tests and templates for different validation needs.
Covered different skews in different protos to reach their landmark.