SUMMARY:

• 10.5 years of industrial experience in Memory and Custom Mask/Layout design.
• Sound understanding of Memory compilers and custom layout designing.
• Good knowledge on analog and mixed signal layouts.
• Good knowledge on matching techniques, shielding, guard rings and deep N - well process.
• Experience on single and dual port SRAM’s, Register files, ROM’s and custom memory layout designs.
• Expertise in developing layouts compatible for usage in muxes(2,4,8,16,32) combinations on the guidelines of the schematic designer.
• Sound knowledge on the DRM(design rule manuals) of different foundaries like TSMC, Confidential, UMC,SMIC, IBM,SILTERA etc.
• Expertise in latest FINFET technologies like 10nm,14nm,16nm and also ranging from 28nm till 180nm.
• Extensive experience in handling the projects which includes the development of the layouts from scratch to instance level and also backend verifications till the tapeouts.
• Expertise in verifying all DFM checks like Pattern checker, LPE, Smartfill, Density and also LVS,DRC,ERC etc.
• Exposure to development of Bitcell and bitcell core arrays which may include discussion with foundary for matching and DRC criteria.
• Worked on all critical periphery memory blocks which includes column and row decoders,sense amp, clock section,datapath designs, IO and control blocks for various projects.
• Experience on tiling, instance level LVS and DRC fixes,LEF generation & verification.
• Expertise on reliability verification flows which include IR drop analysis and EM fixes.
• Well versed with LVS debug using Caliber and Hercules verification tools.
• Good understanding of CMOS Circuits Theory and IC Fabrication.
• Knowledge on lower node DRC constraints,dual,triple and quad patterning
• Knowledgeon Deep Sub-micron issues like well proximity and stress effects.
• Self-motivated, Proactive and Team-oriented person.
• Possess the enthusiasm for work, strong desire to succeed and commitment to continuous skill enhancement that help build confidence and high level motivation to achieve desired results.
• Trained the people on memories and handled the team of 3 to 4 for various projects.
• Understand Electromigration, IR drop & latchup sensitivities for layout.
• Understand DFM tradeoffs and differences on required rules versus optional rules.
• Sound knowledge on floor planning the pitch based layouts, place cells and estimate the complete routing.
• Worked on the layouts designed for Ultra low leakage and high density.
• Implementation of noise reduction techniques for transistors and sensitive signal routings.
• Able to prepare schedule of the project thoroughly and meet the assignments while discussing with schematic designers.
• An effective communicator with excellent relationship building & interpersonal skills. Strong analytical & organisational abilities.

TECHNICAL SKILLS & TOOLS USED:

EDA tools: CADENCE VIRTUOSO till 12.1.2 version

Verification tools: Calibre and Hercules

Operating Systems: UNIX, Linux, Win 2000, XP, Vista.

Scripting language: SKILL

SOFTWARE: MS Word, MS POWERPOINT, MS EXCEL

PROFESSIONAL EXPERIENCE:

Sr. Mask Designer/Lead

Confidential, San diego, California

Responsibilities:

• Close interaction with designers of Confidential, US to excute the project as per specifications.
• Worked on the buffer array design, control blocks.
• Completed backend verifications which includes LVS,DRC,ERC,softcheck,DFM
• DFM includes pattern checker,manufacturability scoring,density etc.
• ECO’s are fixed with respect to the post simulation results.
• Worked on control block which has precharge,clk, addr latch sections.
• Co developed and trained the team of 20 engineers on DFM checks for 10nm FINFET technology.
• Worked on top level backend verifications which includes LVS, DRC and ERC which used latest version of DRM.
• DFM checks include Density checks, Smartfil, DFY checks.

Confidential

Responsibilities:

• Responsible in designing the Bitcell array.
• Close interaction with the team to review and direct them for designing the control block.
• Handled the integration part of the project and also backend verification checks.

SRAM design

Confidential

Responsibilities:

• Handled a team of 3 to execute the project
• GIO’s, Drivers and Control block are executed at Hyderabad and handled the top level integration.
• Worked on top level backend verifications which includes LVS,DRC,Softcheck.

Confidential

Onsite Designer

Responsibilities:

• I was responsible for delivering the complete layout from the scratch various blocks like error amp, ibias, compdriver, fbres, dfx, intref, load cap and control.
• Area estimation, floor plan, placement, and routing.
• DRC/LVS/Density and all LV flow at top level.
• Took care of Electro migration, IR Drops,
• Reliability verifications & QRE sign-off

Confidential

Responsibilities:

• Generation and verification of LEF
• Worked on the phase detector layout and taken care of ECO’s after post simulation results.
• Backend includes DRC,LVS,LEF verifications,ERC etc.

Senior Design Engineer

Confidential

Responsibilities:

• Have executed the Predec block layout from scratch.
• Mux4 and Mux8 backend verifications are executed which includes DRC,LVS.
• It consists of options redundancy on/off and back biasing.

Confidential

Responsibilities:

• Handled mux1 template of periphery cells of mux2 and mux4 combinations.
• Development of sense amplifiers, decoders which are flexible for both mux2 and mux4 as per the requirement.
• DRC, LVS, HLVS, LEF on template level for around 900 combinations.

Design engineer

Confidential

Responsibilities:

• Development of VBIT layout from scratch and taken care of abutment issues.
• Global clock design layout was developed and handled top level verifications.

Design Engineer

Confidential

Responsibilities:

• Worked on the ECO’s of the project as per the design updates.
• Handled all the memory compilers backend verification checks which includes DRC, LVS, HLVS.

Confidential

Responsibilities:

• Design and verification of column decoder
• Layout of Filler cells, bist cells.
• Backend verifications DRC, LVS, HLVS on the top level

Confidential

Responsibilities:

• Design and verification of leaf cells with drc, lvs, dfm clean.
• GDS2,BIF creation for the cells and template level verifications.

Confidential

Responsibilities:

• Stream in GDT to cadence library.
• Draw the schematics according to layout with GDT reference and verification of all the checks.

Confidential

Responsibilities:

• Layouts of the fr cells, verified mux1 fr template, mux2 bist, mux4 mt.
• Template level back end verification is done.