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Principal Engineer Resume

Denver, Co


  • Experienced professional with 10 years of customer facing product management experience with software based application server solutions and 15+ years of digital design/verification of ASIC/ASSP devices and FPGA based solutions.


Product Management: Product Feature Development, Strategy & Planning, ROI Analysis, Customer EngagementVideo Network Systems: SDV, VOD, DOCSIS, Dynamic Ad - Insertion, TWC-ISA & -NGOD protocols

Data Networking: IEEE 802.3, IEEE 802.11, Ethernet, Wi-Fi, Fibre-Channel, Storage Networking

Software / Hardware: ASIC / ASSP / FPGA RTL Design & Verification, System Software Testing

Languages: Verilog & VHDL, RTL & Behavioral HDL, C, Perl, CSH, Tcl/Tk

Synopsys EDA Tools: Design Compiler, Primetime, Formality, VCS simulator, Synopsys Library Compiler & HSPICE

Cadence EDA Tools: Verilog-XL, NC-Verilog & NCSIM simulators and Verisity/Specman

Tanner Tools: L-Edit VLSI Physical Layout Editor, Netlist Extractor, LVS Netlist ComparatorL-Edit Design Rule Checker (DRC), Gatesim Gate-Level Simulator:

FPGA EDA Tools: Xilinx ISE, Altera Quartus, Synplicity

OS & Applications: VMware-Virtualization, UNIX, Linux, Windows, VCOS, Matlab, MS Office, Visio


Confidential, Denver, CO.

Principal Engineer

  • Subject Matter Expert & management for test infrastructure and system test plans for Full QAM sharing environments supporting SDV, VOD and addressable advertising services on ARRIS & Cisco based headend environments.
  • Built automated stress/load test environment to exercise SDV & VOD end-to-end solution at full system activity/session load for 24x7 test periods.
  • Root Cause Analysis and Support of Spectrum Guide SDVclient operation on CPE set top
  • Define & Verify Spectrum Guide SDVclient operation
Confidential, Horsham, PA.

Product Line Manager

  • Managed the Switched Digital Video (SDV), Global Session Resource Manager (GSRM) and Full QAM Sharing (FQS) product solutions. These solutions are Linux based application servers that provide session controlled delivery of MPEG video services (Switched Services & VOD) to interactive customer premise equipment (CPE), set-top boxes, while also performing GigE network & EdgeQAM RF bandwidth management on DOCSIS and traditional HFC communication networks.
  • Successfully proposed & managed programs exceeding $1+ Million in the development & delivery of new SDV / FQS product strategies targeting major cable operators improving near term business unit revenue and forward looking business unit sales while securing the ARRIS SDV & GSRM control plane solutions as the plan of record for future operations within the ARRIS SDV & GSRM customer base.
  • Developed resource cost/budget plans, ROI analysis for review by senior leadership team and defined the marketing/sales product offer/BOM strategy for system software licensing & support framework for next generation SDV, GSRM & FQS system solution upgrades and new deployments.
  • Rebuilt the SDV design & test teams to deliver on the new system software requirements and to provide support for the ongoing product strategy
  • Provided continuous pre & post sale engagement with internal & customer engineering / operational teams to support existing and forward looking product strategies to meet aggressive customer roadmaps and requirements.
  • Managed a team of engineers responsible for functional verification of the Motorola Digital Tuner Adapter (DTA) set-top box and Motorola Cable Advanced set-top Box (ASTB) Platforms.
  • Principal test engineer for the Motorola SDV Embedded Client: Developed, documented and implemented the test strategy to validate functional operation of the Motorola SDV Embedded Client as well as mentored the test team during verification test cycles.
  • Supported SDV, GSRM & ConnectSR application server solutions within internal ARRIS SI&T labs and customer MSO labs & head-ends providing conditional access, provisioning, policy management and session controlled delivery of switched digital video and VOD services to interactive set-top clients and IP based digital devices.

Confidential, Morristown, N.J

Staff Principal Engineer

  • Lead digital designer for mobile wireless Closed-Loop Amplitude and Phase Prediction algorithm used to autonomously correct the non-linear characteristics of a Polar Power Amplifier.
  • Developed RTL synthesizable code to implement the SPCM algorithm on a Xilinx Virtex-II FPGA evaluation platform and the directed simulation test bench/verification environment.
  • Designed the digital control core & mixed signal interface to an analog base band processor core and performed the top level RTL design, verification, synthesis, static timing analysis & timing closure which resulted in the BBIC GSM2 ASIC being a Rev A. Success.

Allentown, PA

Senior Product Design Engineer

  • Verification team leader implementing a Specman constrained random testbench to verify the SPS-3G ASSP device which was a Rev A. success and allowed PMC-Sierra to secure a critical design win on an Industry Leading System.
  • Top Level Design Engineer of the Storage Management Controller (SMC) ASSP device which was completed within a 6 month schedule from concept to tapeout and resulted in first silicon success. The SMC was a MIPS based subsystem with Instruction & Data Cache, Data SRAM, a 4G, 2G, 1G DDR Fiber Channel FC-2 I/F, quad UART I/F, quad Master/Slave TWI I/F, Local Bus I/F and 128 GPIOs.
  • Developed Verilog/VHDL top & module level RTL designs and performed RTL synthesis & Gate equivalence analysis, DFT/SCAN, JTAG, Static Timing Analysis & timing closure, timing back annotation, verification and documentation on Fibre Channel/SAS/SATA storage devices and modules including the QuadPhyFC and TxFIFO module
  • Mentored 3engineers on ASIC design & verification practices and methodology.
  • Lead Verification Engineer for the PSE-160 RevB device, which is a 160 Gigabit Ethernet Crossbar with Optical Network Management ASSP. This PSE-160 device has a 312.5 MHz core clock and contains 64 Mixed Signal SERDES channels operating at 3.125 Gbps (8b10b encoded) or equivalently 2.5Gbps (10b8b decoded), 16 Digital Rx Modules, 16 Optical Network Management Processors, a 64x64 Crossbar Switch-Fabric, and 16 Digital Tx Modules. The PSE-160 was fabricated in a 0.18um CMOS process.
Confidential, Warren, N.J

ASIC Design Engineer

  • Performed the RTL implementation & developed the auto verification testbench for the RTL signal processing datapath for the QPSK / BPSK Demodulator (RxDemod) ASSP on the Home PowerLine Networking Evaluation Platform.
  • Synthesized the QPSK / BPSK Demodulator design into a Altera EP20KTC100 - 2 FPGA for the Princeton Evaluation Platform which consisted of a total of 28 FPGA’s, an MPC860 PowerPC and an analog line isolation and signal conditioning I/F.
  • Delivered the Prototype Platform (Princeton) to the 2000 Cisco HomePlug Field Trials and achieved 6Mbps to 14Mbps sustained transfer rates over a home power line network.
Confidential, Hackettstown, N.J.

ASIC Design Engineer & Product Planner


  • Performed system analysis and planning of strategic Telecom & Datacom ASIC / FPGA based subsystem for packet based networks.
  • Designed, synthesized and verified the RTL based CAM / SRAM co-processor interface module used in the EPOCH ASIC which provided IPv4 Layer-3/Layer-4 Flow Classification and Prioritization addressing CoS and QoS routing for WAN edge router and switch products. The EPOCH MultiLayer Switch was a First Silicon Success and met FCA criteria.

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