CAREER OBJECTIVE:

To work in a challenging environment in a leading organization where I can apply and enhance my skill set in the field of Hardware and Software Design Engineering with a strong intention in meeting the organizations business, quality objectives and providing me opportunities in enabling my career advancement and professional growth.

PROFESSIONAL SUMMARY:

• Having 10 years of experience in the field of FPGA Design and development, Physical Designing, Hardware designing in high speed board and mixed signal design.
• Associated with safety critical and defense oriented projects using RTL coding with Xilinx, Altera, lattices high end tools.
• Expertise in Embedded software development using C, VHDL, Verilog and Assembly
• Experienced in Firmware Development and debugging of 8 - bit, 16-bit and 32-bit microcontrollers, soft-core and hard-core processors using C language
• Extensive knowledge of analog hardware design, digital hardware design, Digital signal processing, signal conditioning, voltage scaling design, power supply design and system design
• Familiar with PCB board layout and schematics, ADC, DAC and DDS design, Ethernet, DDR3, USB, Small Form-Factor Pluggable(SFP), S/PDIF, HDMI Analog and digital design andtransmissionlines and Guiding hardware engineer, PCB designer engineer while designing with high speed boards
• Worked on Spartan, Virtex, Kintex and Artix families devices of Xilinx, Startix and Cyclone families devices of Altera, and different families devices of lattices
• Experience in DFT/DFM techniques for reducing the defects and increasing the productivity
• Experience DRC/DFM Signoff during Physical Design for Provides Faster Time to Closure
• Good knowledge in static timing analysis, clock domain crossing, synchronizers and timing constraints, place and route, translate
• Hands on experience on logic analyzers, oscilloscopes, spectrum analyzers, RTCS(Radio Communication Test Set) debuggers and protocol analyzers
• Experience in implementing Digital filters, DUC(Digital up converters), DDC(digital down converters), Under Sampling, FFT, Noise Cancellation filters, Squelch circuit and Digital signal processing algorithms
• Extensive experience in simulation using Matlab, Simulink and PSPICE
• Experience in development of GUI based applications using VB and Matlab.
• Attended sessions on Signal Integrity, Thermal Analysis, Digital Image Processing at Confidential and on Xilinx at Sandeepani school of VLSI design, Hyderabad
• Work experience in all phases of Hardware/Software Development life cycle
• Expertise in Documentation including design, development and execution of Test plans, Test Strategy and Test cases.
• Ability to learn new technologies in short span and implement independently, good functional and technical documentation skills.
• A team player with strong organizational abilities and prioritizing skills
• Provided technical and functional s to the new joiners at Confidential and SRM Technologies
• Guided Juniors while on work on both technical and functional fronts

TECHNICAL SKILLS:

Languages: C, VHDL, Verilog, ASSEMBLY and MATLAB

Hardware Design: Analog and Digital Circuits.

Bus and serial Protocols: USART, GPIB, SPI, I2C, Ethernet, SERDES, DDR, HDLC, OPB, AMBA, Avalon, Arnic 429 and 1553B.

Tools: and Utilities Processors: ZYNQ, Micro Blaze, Nios, power pc, ARM,8085. controllers: PIC, MSP430, AVR, ST controllers and 8051( C).

Compilers: MPLAB, CCS, Turbo C and ANSI C.

Debuggers: GDB (GNU Debugger) XMD prompt, BFM, ModelSim, Chip Scope, Signal tap, System Vision and Constraints.

Scripting Languages: Tcl, perl, Matlab and Visual basic

RTOS: XilKernel (POSIX).

IDE: Xilinx tools (EDK, ISE, Chip scope & system Generator), Altera tools(Quartus, Qsys, SDK), lattice tools, Simulink, Cadence Allegro, Concept HDL, Dx designer, Altium and CADSTAR

IP cores development: 82c54 Timer chip

EXPERIENCE SUMMARY:

Confidential

Team lead

Responsibilities:

• Simulation and development of DSP algorithms using Matlab, Simulink.
• Firmware development of peripherals like ADC, DAC, Ethernet, Memory, LCD.
• Design and development of digital filters, numerically controlled oscillator.
• Digital and Analog hardware designing, board bring up and validation
• Design and stimulation of preamplifier, filters using PSPICE.
• Designing of schematics using Cadence Allegro. schematics designing using Orcad
• PCB routing using Cadence Allegro and Signal Integrity using Hyperlinks software.

Tools: Xilinx ISE, chip scope, Matlab, Simulink, PSPICE and Cadence Allegro

Confidential

Team lead and Developer

Responsibilities:

• Simulation and development of DSP algorithms using Matlab, Simulink
• Firmware development of peripherals.
• Gathering the requirements on the basis of functionality from the client directly
• Involved in HDL Coding for the calculation of the speed in KnM/hr using the incoming Log Data
• Interfacing of timing and status signals from this card to other cards
• Guiding PCB team with placement, routing guide line
• Involved in real time system level testing in Radars

Tools: Xilinx ISE, chip scope, Matlab, Simulink, PSPICE and Cadence Allegro

Confidential

Developer

Tools: Xilinx EDK (Embedded Development Kit), Xilinx SDK (Software Development Kit) and XilKernel, chip scope, Matlab and Orcad.

Responsibilities:

• Implemented XilKernel (POSIX Compliant) to have Real-Time control on process using ROUND ROBBIN AND PRORITY SCHEDULING CONCEPTS, MULTITHREADING concepts in FPGA.
• Implemented DUAL PROCESSOR and Multicore processor.
• Implemented range tracking, Doppler tracking algorithms and firmware of peripherals.
• Interfacing of various peripherals using different Busses (AXI, PLB4.6, PLB3.4 and OPB bus).
• Implemented Dynamic Allocation for Scratch-Pad Memory (at run time). static timing analysis, clock domain crossing, synchronizers and constraints
• Design and development of pulse repetition frequency.
• Physical design of Block level synthesis and analysis for meeting timings
• Digital and Analog hardware designing, board bring up and validation
• Designing of schematics using Cadence Allegro.
• Simulation of DSP concepts using Matlab

Confidential

Developer

Responsibilities:

• Simulation and development of DSP algorithms using Matlab, Simulink.
• Firmware development of peripherals.
• Coding using VHDL and c language
• GUI development using visual basic
• Design and development of digital filters, numerically controlled oscillator
• Digital and Analog hardware designing, board bring up and validation
• Design and stimulation of preamplifier, filters using PSPICE
• Designing of schematics using Cadence Allegro schematics designing using Orcad
• PCB routing using Cadence Allegro and Signal Integrity using Hyperlinks software

Tools: Xilinx ISE, EDK, chip scope, Matlab, Simulink, Visual Basic, PSPICE and Cadence Allegro

Confidential

Developer

Tools: Xilinx EDK (Embedded Development Kit), Xilinx SDK (Software Development Kit) and Xilkernel, chip scope, Matlab and Orcad.

Responsibilities:

• Developed C-Language programs in Xilinx SDK, to interface sub-systems with radar control computer.
• Interfaced Components ADC, DAC, DDR, Ethernet, SDRAM, FLASH and DDS with Micro Blaze processor (Developed firm ware for these peripherals) and did performance testing.
• Development of algorithms for the seeker computer to interface with digital signal processing unit.
• Developed a GUI to check the performance of the system and to interact with radar controller using Visual Basic.
• Design and Development of hardware for RADAR Controller and Simulator.
• Designing of schematics of simulator using Orcad.
• Simulation and analysis at block level has been done for meeting the timing.

Confidential

Team lead

Responsibilities:

• Development and Simulation of custom cores.
• Design and development of wrapper logic for handling the low speed peripherals.
• Designing of schematics using Cadence Allegro.
• Schematics designing using Orcad
• PCB routing using Cadence Allegro and Signal Integrity using Hyperlinks software.

Tools: Altera Quartus ii 14.1, ModelSim, Qsys and Cadence Allegro

Confidential

Team lead

Responsibilities:

• development and Simulation of Glue logic using ModelSim.
• Firmware development of peripherals like, RTC, Ethernet.
• Design and development of digital filters, FFT.
• Digital and Analog hardware designing, board bring up and validation
• Designing of schematics using Cadence Allegro.

Tools: Xilinx ISE, EDK, chip scope, ModelSim and Cadence Allegro

Confidential

Team lead

Responsibilities:

• development and Simulation of Glue logic using ModelSim.
• Digital and Analog hardware designing, board bring up and validation
• Designing of schematics using Cadence Allegro.

Tools: Xilinx ISE, EDK, chip scope, ModelSim