Contractor Resume San Jose, CA - Hire IT People

OBJECTIVE:

To seek a challenging position as a Senior Mask/ Layout Designer

TECHNICAL SKILLS

Layout Tools: Cadence Virtuoso Opus layout (VXL) editor

Verification Tools: Dracula / Diva / Calibre / Hercules/ Assura and PVS

Operating Systems: UNIX on Sun Workstation

Languages: Basic, Pascal

PROFESSIONAL EXPERIENCE

Contractor

Confidential, San Jose, CA

Responsibilities:

Responsible for the metal option of 0.18 - um technology clock chip to achieve low phase noise inside clock buffers and reduce any possible coupling and skew.
Performed RF analog layout of 0.13-um technology from cell level to block level.
Worked on deep submicron CMOS 0.28-um technology high frequency analog/mixed signal layout of CML circuits, RF components, including metal/metal capacitors, VCOs, High Speed IO Buffers, Op-Amps, cascoded current sources.
Utilized a variety of analog/mixed signal layout techniques for critical net matching, noise reduction/ isolation such as Common Centroid, Interdigitation, Dummies, critical route shielding, triple well layout, ESD device and cell layout and guard ring layout methods.
Has experience in Cadence Virtuoso Opus layout (VXL) editor 6.1.6

Contractor

Confidential, San Jose, CA

Responsibilities:

Built custom layout of analog/mixed signal, me/O and standard cells in CMOS 20-nm technology wif ESD protection and latch-up prevention.
Shielded critical signals to ground/power line for noise reduction and added guard-ring around critical devices to keep noise from getting into substrate.
Worked on custom layouts of RF high speed analog/mixed signal design using CMOS/SiGE BICMOS of 180/90-nm technologies.
Completed layout of the BIAS, Data Buffer, Op-Amp, TX-Mixer, RX-Mixer…
Responsible for custom layouts of high speed analog/mixed signal designs in sub-micron CMOS 0.25-um technology for Test Chip and Wireless Charger.
Routed signals, powers, and run verifications at the SERDES block level.
Using Calibre to fix antenna/density/IR drop/latch-up/ESD errors.

Senior Layout Designer

Confidential, San Jose, CA

Responsibilities:

Worked on various analog/digital blocks, planned critical signals, power bus arrangement, global routing and interconnections.
Planned and built the analog/mixed signal layout blocks that required matching such as clock circuits, Op-Amp, Oscillator Buffer, Charge pump, High voltage generator, Phase Frequency Detect and Loop Filter in PLL for 50/35/29-nm technology.
Built IO pad libraries, prepared for ESD protection, latch-up prevention, guard rings and IO Pad arrangement.
Built inline and staggered templates 5V tolerant General Purpose IO wif ESD protection for 0.18/0.15/90/65/45-nm technology wif different types of metal options.
Using via programming (metal options) to create different 300 inline and 700 staggered IO cells for each library.

Senior Layout Designer

Confidential, Sunnyvale, CA

Responsibilities:

Built IO pad wif ESD rules to work wif multi voltage supply.
Built a programmable architecture to produce different type of chips by changing only single metal mask.
Performed High Voltage mixed signal layouts in analog/digital circuits and worked on various analog/digital blocks.
Responsible for the layout of 0.35-um technology 5-Volt tolerant me/O cells wif ESD protection and latch-up prevention.
Created me/O templates in 0.25/0.18-um technologies wif metal programmability.