SUMMARY:

• Architected Low Power verification for multi - power domains SOC.
• Have thorough understanding of different verification strategies suited for today's applications.
• Have extensive experience in planning, implementation and execution of the projects.
• Developed test plans and UVM based verification environment from scratch
• Developed SystemVerilog models for Mix Signal validation.
• RTL Design and Design Verification with extensive start to finish project experience.
• Hands on experience on block level, gate level, and chip level verification.

EXPIRIENCE

• Designed agents in UVM environment for Low Power verification combining UPF and UVM
• Developed UVM based verification (PCIe - NVMe) for SSD controller (Dynamic Wear Leveling, AES crypto block, ETC)
• Verified Low Power Design using MVSIM, MVRC (SNPS), and Conformal LP (CDNS), wrote UPF scripts for the low power verification and synthesis.
• Transferred RTL from ASIC to FPGA for emulation.
• Verified data link layer for PCI-E.
• Resolved LP related Multi-mode, Multi-corner MMMC, STA timing corners and PVT issues.
• Transformed verification components from OVM and VMM to UVM
• Developed UVM infrastructure for block and partition level verification
• Wrote scripts for register layer modeling in the Cadence environment
• Performed static timing analysis (STA) using PrimeTime
• Designed power controllers for low-power design. Used Spyglass for linting
• Performed logic synthesis using Synopsys tools (design and power compilers)
• Wrote scripts for low power design using UPF
• Designed verification system for RapidIO using RVM (Vera) and SystemVerilog
• Wrote SystemVerilog assertions (SVA) for functional coverage
• Verified multi-channeled low-power DMA for controllers
• Verified DDR3 interface using SystemVerilog (VMM)Designed DSP blocks (FIR/IIR, FFT)
• Designed High Speed Serial Link (6 GHz) using 65nM technology (IBM)
• Designed CACHE controller (MESI and MOESI) for MPU.
• Designed cryptography units (DES, 3DES, DESX, SHA, AES)

CAE EXPERTISE AND TOOLS:

Tools: tcl, shells, awk/sed/perl, python, make, C, C++

Languages/HVL: Verilog, SystemVerilog, VHDL, SVA, PSL

Synopsys: DC, PrimeTime, TetraMAX, VCS, MVSIM, MVRC, Spyglass, VC LP

Cadence: Incisive NC, Incisive Formal (LEC), Conformal LP

Mentor: ModelSim, Questa, Fastscan, Formal PRO (LEC)

PROFESSIONAL EXPERIENCE:

Confidential, CA

Sr. Consultant

Responsibilities:

• Developed verification environment (UVM) for SSD (DWL) block from scratch.
• Designed verification environment for security control module (SHA, AES128)
• Developed UVM base components for AXI4 - lite and AXI4 slave interfaces.
• Confidential, CA Sr. Principal Engineer
• Developed verification methodology and scripts for low power SOCs (Arm/Cortex) based on UVM (SystemVerilog) and IEEE standard (UPF2.1)
• Designed verification environment (UVM) for high speed memory controllers (DMA)
• Optimized UVM scripts for migration from UVM1.1 to UVM1.2 to reduce simulation time for VCS environment
• Closed coverage measures to identify verification holes and to show progress towards tape-out

Confidential, San Jose, CA

Sr. Staff Engineer

Responsibilities:

• Wrote SVA scripts for functional verification and coverage
• Build effective constrained random verification environments from scratch.
• Developed memory block s verification environment using UVM.
• Wrote CRV script for regression and functional verification (UVM)
• Designed verification scripts to improve coverages (code and functional)

Confidential, San Jose, CA

Verification Consultant

Responsibilities:

• Developed methodology for low power devices' verification
• Verified Low Power Design using MVSIM and MVRC, wrote UPF scripts for low power verification and synthesis.
• Developed UVM based Power Centric verification for the clock - gating, MVMF, and Power Domain based designs
• Wrote agents (UVM) for USB3 verification (Reconfigurable IP)
• Developed verification environment for Journal Engine (SSD)
• Verified Multiprocessor Memory switch using UVM1.1
• Rewrite VerilogA mix signal models using SystemVerilog and DPI (C++)

Confidential, San Jose, CA

Principal ASIC Engineer

Responsibilities:

• Developed verification environment for reconfigurable write channel using UVM (1.0ea)
• Designed agents (UVM), and UVM verification related classes: scoreboard, env, virtual sequence and sequencer using Cadence environment.
• Wrote scripts for register layer modeling using RDL (Register Description Language) and UVM RGL.
• Verified 3D processing block using DPI (Questa) and OVM
• Wrote SVA script for error detection and functional coverage
• Developed verification environment using NC Incisive (Cadence) and OVM
• Wrote test suites for ARM using AXI/APB/AHB interface using Questa (AVM)
• Designed verification system for Ethernet using Vera (RVM) and SystemVerilog
• Wrote SystemVerilog assertions (SVA) for functional coverage
• Developed verification environment for the router blocks using Vera
• Designed low power communication products, reduced dynamic power up to 30%
• Designed verification environment for PCI interface (Xilinx Spartan 2 XC2S15)
• Designed high speed serial link modules using 65 nM technology (VHDL)
• Validated performance. Wrote models for mix-signal simulation
• Developed verification environment and constraints for ECC verification using different statistical models for error insertions

Confidential, San Jose, CA

Sr. Engineer/Project Lead

Responsibilities:

• Designed SystemVerilog models for Viterbi and Turbocode based communication blocks.
• Designed Cache Coherency protocol checkers.
• Wrote assertions for functional coverage based verification
• Verified PCI - E control block (DMA) using SystemVerilog VMM
• Modeled external interfaces using SystemVerilog (NC Incisive).
• Designed high speed channels (800Mbyte/sec) and cache control block (MESI)
• Developed block and system level testbenches for cryptography using Vera.
• Designed low-power systems for wireless devices
• Verified hardware encryption protocols: DES, 3DES, AES, SHA, ECC
• Designed pixel manipulation module for 3D graphic using Module Compiler

Confidential, San Jose, CA

Sr. Design Engineer

Responsibilities:

• Designed XA controller and serial communication controller’s systems/units for 16 bit microcontrollers (I2C, SDLC/HDLC, and byte oriented protocols)
• Wrote Verilog and VHDL scripts for synthesis and verification

Confidential, Menlo Park, CA

Sr. ASIC Engineering Specialist

Responsibilities:

• Developed T1/E1 interface units for communication systems
• Designed video compression DCT (Discrete Cosine Transform) block
• Designed MPEG2 system for video - on-demand
• Verified high speed video compression block
• Manage of international team of ASIC designers.
• Designed multiple processors and interface blocks
• Participated in the SPARC v9 spec definition
• Verified adaptable interface block for the SPARC workstations