Researcher (ASIC Design) Resume VA - Hire IT People

OBJECTIVE:

Seeking a position in the ASIC/VLSI domain which enables me to utilize my knowledge in ASIC design, layout, and CMOS technology to maximize an organizations performance.

SUMMARY:

Professional experience of 3.5 years in Embedded software domain.
Experience in ASIC design from RTL design to backend implementation using Synopsys toolset.
Worked on Synopsys: Design Compiler (Synthesis), Primetime (STA), ICC (Floorplanning), Clock tree synthesis, Place and route in 32/28nm technology node and exposure to 14nm technology.
Low power/leakage reduction techniques using Primetime (ECO) and CMOS design fundamentals.
IR drop analysis and reduction on Synopsys PrimeRail and Apache RedHawk.
Have experience with power aware verification (with CLP - using CPF format).
Standard Cell Layouts using Virtuoso Layout Editor. DC and Transient analysis using HSPICE.
Proficient in C, firmware programming, mobile app (J2ME) and android code development.
Worked on different OS including Linux, Solaris.
Experience in scripting using Tcl, Python, and shell.
Programmed on 8/16/32 bit microcontrollers worked on interfacing with I2C, SPI, CAN, UART.
Received “Pat on the back” award by senior management to recognize work done.
Received customer satisfaction award from the client at SigmaEdge.

SKILL:

Domain: ASIC Physical design and Layout, ASIC frontend development and Embedded systems.

EDA/CAD VLSI Tools: Synopsys - Design Compiler, PrimeTime, IC Compiler, PrimeRail, StarRCXT, HSPICE, TCAD. Apache Redhawk, Xilinx ISE Suite, Cadence Virtuoso Layout Editor.

HDL/Programming/Scripting: Confidential, Verilog, SystemVerilog (basic), C, C++ (basic), Tcl, Python, LUA, shell.

Hardware: Various 8/16/32 bit microcontrollers.

Other tools: SMTSIM, Eclipse IDE, Visual Studio, Keil, ClearCase, Assembly, Tanner (Layout), OpenTimer, MASM, PHP.

PROFESSIONAL EXPERIENCE:

Confidential, VA

Researcher (ASIC Design)

Responsibilities:

Performed physical design related tasks including block floorplanning, P&R, Physical verification ( Confidential, LVS), RC extraction for 32/28nm technology node.
Scripted a CTS algorithm which uses useful skew to reduce Dynamic IR drop due to simultaneous switching of cells in the design. Tools: ICC, RedHawk, TCL.
Synthesized IWLS-benchmarks with ECO power reduction and constructed a PDN with flip-chip tech.
Dynamic power analysis and leakage recovery using VT swapping and Voltage drop analysis.
The IR drop reduced by 40%, improving power efficiency by 25% and peak current was reduced by 30%.
Created an automation process for the entire physical design process using a makefile.

Confidential

Software Engineer

Responsibilities:

Developed program-info module from scratch including various actions, context switches and UI development.
Developed VOD and HD canvas scaling for program information, DVR and UI screens.
Performed hardware prototyping and debugging and device drivers design and implementation.
Used subversion to keep track of software development.

Platform: C, Embedded C, Lua, VZPAL

Confidential

Research Understudy

Responsibilities:

Scripted an algorithm to assign polarity to clock buffers and choose opposite buffer type from its parent buffer.
Extended existing algorithms in partitioning, recursive min-matching for polarity assignments.
Synthesized for Confidential circuits in Design Compiler and did HSPICE transient simulation.
Average peak current and delay variations were reduced by 35% and 38%.

Confidential

Software Engineer

Responsibilities:

Designed Multiplier accumulator (MAC) units in verilog. RTL to gate level netlist synthesis in DesignCompiler, STA and timing closure in PrimeTime, RC extraction in StarRC and backpropagation in Tcl.
Floorplanning, P&R, develop timing flows, setup & hold optimizations script automation for sign-off.

Confidential

Software Engineer

Responsibilities:

Obtained maximum and optimum operating frequencies keeping area and power consumption at a minimum.
P&R, clock tree synthesis, floorplanning, ECO, POCV, AOCV timing flow, power analysis in PTPX.

Confidential

Layout Editor

Responsibilities:

Completed layout from the given Spice Netlist for the basic logic gates, D-Latch, and T-Latch.
Maintained metal pitches, used single metal layer, followed half Confidential rules.
Developed OMD v2.0 cipher using Confidential and wrote test benches and tested using C-code provided by OMD developer. Tool used Xilinx ISE.

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