SUMMARY
Skilled electrical engineering professional offering 15 years of broad experience, a unique blend of technical skills and software engineering experience

• Languages: (System) Verilog (RTL), VHDL (RTL),C/C++, STL, SystemC (ESL), TCL, Visual Basic, assembly(including x86, ARM and 8051), embedded systems/firmware
• FPGA: Altera, Xilinx, Actel
• Networking/Communications: Ethernet, DSL, VoIP, Wireless (802.11), POTS (Telephony)
• Hardware: Schematic Capture, Logic Analyzers, Oscilloscopes, Spectrum Analyzers, PCB design, EDA, Test Automation/Scripting, PCI, DDR2, PC architecture, Test plan development
• Defect Tracking/Version Control/QA: Clearcase, PVCS, Subversion (SVN), Rational ClearQuest, Rational Quality Manager, Test planning, Scrum/Agile
• Office: Word, Excel, PowerPoint, Access (relational database), Microsoft Project
• Operating Systems: Windows, Linux, AIX, MacOS

Many years of C/C++ programming/testing in multiple environments

• Chip performance verification using SytemC/C++
• ESL chip modeling using SystemC/C++
• Creation of Powerpoint slides for C/C++ training
• Experience using STL with C/C++

Experience in Relational Databases

• Use of Microsoft Access for queries and reports

Testing and QA experience

• White box testing of code including C++ software written by others
• Scriping & automation experience including TCL/TK and Unix
• Experience in Scrum/Agile

EMPLOYMENT EXPERIENCE

Confidential, Austin, TX 2010-present

QA Testing for Enterprise Server Systems

• Perform functional testing of server software, firmware, and Java based management consoles. Follow and create test plans for functions including partition management, system maintenance, and server repair. Use of ClearQuest for defect tracking and Rational Quality Manager for test planning. Execution and editing of Unix scripts.
• Use of Scrum/Agile process

Senior Consultant for consulting engagements with customers

• Performance verification engineer for video co-processor. White box testing of code written by outside vendor. Created instrumentation, performance reports, and test cases using SystemC/C++ and TLM. Used Microsoft Visual C++ for development and debug environment. Model used for performance modeling and early software development.
• Created training PowerPoint slides and program samples for training in SystemC/C++.
• Created VGA image/graphics software emulationusing Imagemagick for imaging functions (magnify, rotate, etc.) and PicoTK for raster functions. Used SystemC/C++. Debugged code using Linux gdb and ddd debugger.
• Created ESL demo platforms representing Wi-Max and portable image processor SOC's for major EDA vendor at Xtreme-EDA. Used SystemC/C++ and TLM.

Clients included Confidential

• Created and executed test plans for complete feature coverage of POS software ahead of project schedule resulting in 20% cost savings at Oracle.
• Designed software with DES (Data Encryption Standard) using C/C++ to increase feature test coverage of SSL ASIC by 10% on schedule.
• Maintained, debugged, and created new features of VHDL behavioralFBDimm model with DDR2 interface for server system verification effort at IBM.
• Created business proposal for PC based chemical process control system.

Member of Technical Staff
Post silicon engineering of communications ICs.

• Lead engineer in creating specification documents for ADSL test automation based on DSL Forum WT-62 (DSL Modem Interoperability Requirement Specification)
• Performed test automation and measurements to support design bid of telecom IC with external partner for VoIP IADresulting in design win and $2 million in future business at AMD/Legerity. Used and debugged internally developed PCB.
• Developed TCL test script for test validation, automating tests, and debugging IC for telephony/communications which features integrated voice/data chip set which increased test coverage and failure duplication rate ahead of project schedule by 10% at AMD/Legerity.

Advisory Verification Engineer
Verification/Test of GPU ASICs.

• Constructed models and executed test cases for emulation and white box testing of VHDL code for GPU ASICs on Quickturn system.
• Designed and debugged Altera FPGA with PCI interface for custom PCB to increase test coverage of video port on emulated graphics chip on schedule. FPGA send raster images to emulated graphics card to simulate video.
• Created test cases on image rendering and raster display for verification of emulated graphics ASICs using C/C++on schedule.
• Created test plan for verification of GPU ASICs.

Manager/Senior Engineer
Design/Test/Sustaining engineering of enterprise networking products

• Manager in newly formed sustaining engineering group in support of enterprise network products at 3Com.Resolved issues and put new processes in place with marketing and out-sourced manufacturing and compliance.
• Designed hardware/firmware/PCB of hand held network tester/protocol analyzer for both token-ring and Ethernet networks on schedule and generated $2 million in revenue at 3Com Corp. Used C for development. Debugged in assembly language with in-circuit emulator.
• Design of embedded system (ASIC, PCB, and firmware usingC) for networking product resulting in $3 million in annual savings at 3Com Corp. Used C for development. Debugged in assembly language with in-circuit emulator.
• Experience in engineering management/leadership including project management and outsourced manufacturing including PCB and engineering revision/change orders.

Senior Engineer
Design of ASICs for customers and EDA software engineer for ISA (IBM AT) accelerator card.

EDUCATION

MA