CAREER OBJECTIVE

To join a center of expertise specializing in areas of image-video-speech processing and pattern recognition for embedded applications.

TECHNICAL SUMMARY

Fifteen years of hardware-software experience in the fields of digital video/audio signal processing, image processing, and pattern recognition for embedded & desktop applications. Developed Video-Audio Watermarking IP for HD set-top boxes and HD/Blue-Ray DVD recorders/players. Developed embedded hardware-software for satellite/terrestrial set-top boxes (using DirectTV-DVB-ATSC transport layers, MPEG/H.264 ML@MP-HL@MP video layers and MPEG/AC3/AAC audio layers). Designed an interactive multi-media authoring system using MPEG/H.264 Video-Audio & JPEG for Desktop applications. Designed several industrial-security applications using high performance MPEG4 IP based security cameras. Designed a pattern recognition system for dimension analysis of miniature objects. Took from concept to design a bit-mapped on-screen-display processor, progressive scan processor and a multi-sync/geometry scan processor using an ARM6 embedded RISC core.

PROFESSIONAL EXPERIENCE

Senior Embedded Audio Signal Processing Engineer: Confidential,San Diego, CA.......Jan 2009 till Present.

• Responsibilities include developing audio watermarking algorithms (embedders & detectors) and porting them on DSP based systems (HD & Blue Ray DVD recorders & players) using a combination of embedded C and vendor provided assembly routines.
• Developed a studio based multi-DSP (4) embedder using the Motorola DSP 56300 to embed a watermark in 8 parallel audio channels (dolby 7.1 channels) for live AV recording.
• Developed a subsequent detector using Analog SHARC ADSP-21369 for detecting the embedded audio watermark in 8 parallel audio channels.

Senior Embedded Software Engineer: Confidential,San Diego, CA.......Jan 2008 till Jan2009.

• Responsibilities include developing software for high end Network Processors (RAZA, CAVIUM) which take in a 2-3 GB ISDN transport multiplex and generate several thousand mpeg flows at varying bitrates which feed into QAM modulators.
• Developed a Mpeg Transport Stream Redundancy Simulator on a x86 VxWorks Embedded Platform (to be ported on a network processor) which was capable of analyzing a multitude of TS stream failures from an ISDN line and providing several redundancy measures for QoS to end users.
• Developed a software solution for the Broadlogic BL81000 80 stream backend MPEG decoder for cable operators to provide a seamless solution for transitioning to all digital services.

Senior Embedded Video Signal Processing Engineer: Confidential,San Diego, CA.......Jan 2007 till Jan 2008.

• Responsibilities include developing Video-Marking technology for copy-protection of Digital Video Transmissions & porting this technology across Linux OS based IP, Satellite & Cable Settop boxes from industry standard chipset manufacturers. Familiar with TI-DaVinci ARM & MIPS based Linux (system on a chip solutions) and kernel / user-space Linux development in these environments.

Senior Staff Applications Engineer: Confidential,San Diego, CA.......August 2005 till Jan 2007.

• Responsibilities include application development and support of Conexant Frontend (DVB-S, DVB-S2, DVB-T, ATSC) Silicon for Satellite and Terrestrial markets.

Senior Electronics Design Engineer: Confidential,San Diego, CA.......July 2004 till August 2005.

• Development of TI Multi-media DSP DM642 Firmware and FPGA based Hardware for MPEG4 (IP based) Machine Vision Camera Systems and SMART Security Camera Systems. The project involves motion detection (using motion vectors) and voice detection (using impulses) on the DM642 with all the subsidiary camera control hardware implemented on an Altera FGPA / Motorola HCS08 platform. Standard Protocol stacks from TI (TCP/IP, UDP & RTP/RTSP) and Video Security IP (VSIP) from ATEME has also been used.
• Development of software / hardware for 1394 based Industrial Camera Systems supporting different sensors for VGA, SXGA and Partial Image Formats. These systems are developed using Motorola M-Core and HCS08 processors, TI 1394 PHY chipsets and Altera FPGAs.

Senior Applications Engineer: Confidential,Schaumburg, IL.......Jan 96 till July 2004.

• Developed a Hard Disk Drive interface driver (DVB/DIRECTV STB) using the Ultra DMA mode to read/write transport or PES packets to a standard ATAPI hard disk (e.g. Maxtor) along with a basic file system for indexing sequences and audio frames stored on it to support various trick modes like FF & FB during playback.
• Participated in the development of a network rack mounted DVB compliant MPEG decoder capable of handling transport bitrates ~90mbits/sec.
• Developed Ethernet based tool for validation scripts written for ST HDTV platform.
• Prototyped a simple digital PVR (personal video recorder) application using a ICOMPRESSION Labs encoder and a ST decoder. The application was capable of digitizing a live source (single A/V program), compressing/packetizing it into a typical MPEG2 transport stream, storing it on a Hard Disk, and playing it back using the decoder.
• Developed a integer complex library to give DSP functionality to the ST20 32 bit RISC core.
• Involved in the hardware & embedded software design cycles of satellite and cable settop boxes using ST chipsets for QPSK/QAM demodulation, MPEG2 Transport de-multiplexing, MPEG1/2 Video Decompression & MPEG/AC-3 Audio decompression.
• Worked on Audio/Video & Subpicture applications for DVD boxes.
• Designed a toolset for General Instruments digital cable settop box. The toolset consisted of libraries for the 64/256 QAM frontend, OOB downstream processor, the upstream return channel and the transport/AV decoder.

Concept Engineer: Confidential,Glenview, IL.......July 93 till Jan. 96.

· Designed a bitmapped On-Screen-Display (OSD) processor, for generating VGA quality graphics for high resolution digital TVs. It had a built in DMA controller for its external video memory and interfaced to an external PC via an intel 8052 core built inside it.

• Designed hardware/software for a multi-sync scan processor (used the ARM6 RISC processor as an embedded controller) used for digital convergence in high end monitor/TV applications. The ARM6 along with its coprocessor (FPU) were used to do 3rd order regressions (cubic-spline) on stored convergence coefficients and fundamental waveforms. The results were then transmitted to an in-line processor which interpolated the data in the horizontal and vertical directions and generated correction waveforms through interpolative D/As. Horizontal frequencies from 15 to 70 KHz were supported for all types of video sources.
• Developed software compression/decompression modules for 24 bit video (moving JPEG, intra/inter frame coding using RLE) and 16 bit audio (ADPCM) stored on random access media (hard drive, etc.).

Creative Signal Processing Confidential,India ......Jan. 92 till July 93.

• Developed an interactive multi-media authoring system using MJPEG Video & ADPCM Audio. The authoring system was capable of compressing/decompressing True Color video and 8/16 bit stereo audio. Also various graphic primitives were developed for constructing 2-D/3-D graphics. Device drivers for most existing graphics processors were written. The authoring system also had the capability of interfacing to an frame grabber, speech capture board and speech playback device.
• Designed a pattern recognition system for the dimension analysis of light petroleum gas (LPG) valves. Techniques such as contour tracing, edge detection and normalized co-relation were used. Accuracies of 10 microns (using fractional interpolation, 1 pixel = 4 pixels) could be obtained using a standard SONY CCD camera having a resolution of 512x480 pixels.

Concept/Design Engineer: Confidential,Glenview, IL.......May 90 till Dec. 91.

• Designed a new micro-controller using the Intel 8052 as an embedded core for use in digital TVs. The embedded core was used to control various peripherals like IR (infrared) decoder, PLLs and PWM/s.
• Developed a progressive scan processor for NTSC component (YUV 4:1:1 & 4:2:2) video.
• Developed various adaptive algorithms (SHARF & lattice structures) for ghost cancellation in NTSC.
• Wrote a behavioral language model in VHDL for an audio processor with integrated Sigma-Delta A/Ds..
• Designed adaptive noise immune multi-sync digital phase locked loops for vertical and horizontal sync detection in multi-sync monitors.

Graduate Research Assistant: Confidential,USA.....Aug. 88 till May 90.

• Designed two adaptive parallel digital signal processor (DSP) structures for low-level image processing applications. DSPs used were the TMS320C30 and DSP56000.
• Developed digital image processing techniques for fault analysis of semi-conductor wafers.
• Implemented the 2-D discrete cosine transform using the TMS320C30 for image compression.

Internship: Confidential,INDIA.......May 88 till Aug. 88.

• Developed software modules for stepper motor control in 3 axis robots.

EDUCATION

Master of Science in Electrical Eng. with specialization in signal processing:

Bachelor of Engineering in Industrial Electronics:

TECHNICAL SKILLS

• Good know-how of all the DSS/DVB/ATSC specifications & their fundamentals.
• Programming various Motorola & TI Digital Signal Processors using C to assembly cross-compilers.
• Programming ARM & ST20 RISC engines.
• Parallel Processing and Multi-threaded Video & Audio applications using Win32 on Windows NT.
• Building embedded image processing applications for WinCE devices using Platform Builder.
• Behavioral language modeling using VHDL for digital systems.
• Concept Realization using Matlab’s Image & Signal Processing Toolkits.
• Working Knowledge of 3-Dimensional Imaging Techniques like Surface & Volume Visualization as applied to Medical Imaging Applications.

· Knowledge of FPGA (Xilinx) design methodologies.

OTHER ACHIEVEMENTS

US Patents:

• Multi-standard synchronizing signal recovery system.
• Single wire bus protocol for multi-master/slave configurations.
• Digital modulation/demodulation of FM signals.

Papers:

• Fast implementations of image processing algorithms using parallel-distributed Digital Signal Processor architectures.
• Simplified Micro-controller-FPGA platform for Digital Signal Processing.
• Watermarking Video in a STB environment.
• Watermarking Audio in a STB environment.