SUMMARY

Skills :

Key Skillsets:

Analog and Mixed signal IC design

Schematic Capture tools:

Cadence Virtuoso

Simulation tools:

Spectre, H-SPICE

Layout tools:

Cadence Virtuoso

LVS/DRC tools:

Assura LVS/DRC

Programming Skills:

Basic knowledge of perl,tcl, OCEAN

Publication/Patents :

EXPERIENCE Summary:

August-2010 – till date: Working at Confidential,India as a Senior Analog Design Engineer.

March-2008 – July-2010: Worked at Confidential,India as a design engineer.

Oct-2006 – August-2007: Worked at Confidential,as Mixed Signal Engineer.

EXPERIENCE PROJECT Summary :

1. Low power low voltage and highly accurate bandgap reference :
Designed highly accurate bandgap reference in 40 nm CMOS process with an untrimmed
error of less than 1.5% at supply voltage of 1.1V. Circuit consumes less than 10uA
current.It also consists of circuit which triggers the signal when bandgap reference output
settles within +/- 13%. The silicon validation of bandgap reference is done to capture an
untrimmed accuracy, current consumption, temperature coefficient, output ripple
amplitude and startup time.

2. Low area and high accuracy CMOS Oscillator:
Designed CMOS based RC oscillator circuit in 90 nm CMOS process with an accuracy of
greater than +/-2.5% (post-trimming). Typical oscillator frequency is 40MHz with startup
time of less than 10usec. Total power consumption of circuit is less than 20uA.Frequency
peaking is < 5% (During startup). Highly insensitive to supply variation and supply
rejection of greater than 40 dB for all frequencies from 0 to 1GHz at 1.1V Supply.

The silicon validation of oscillator is done to capture accuracy, startuptime, peaking,
current consumption PSRR and temperature coefficient.

3. Low power, low area and supply independent RC Oscillator :
Designed CMOS based RC oscillator circuit in 40 nm CMOS process with an accuracy of
greater than +/-2.5% (post-trimming).Typical oscillator frequency is 100MHz with startup
time of less than 5usec. Total power consumption of circuit is less than 50uA.Frequency
peaking is < 5% (During startup). Highly insensitive to supply variation and supply
rejection of greater than 40 dB for all frequencies from 0 to 1GHz at 1.1V Supply.

The silicon validation of oscillator is done to capture accuracy, startuptime, peaking,
current consumption PSRR and temperature coefficient.

4. Dual mode low power, low area and supply independent RC Oscillator:
Designed CMOS based RC oscillator circuit in 40 nm CMOS process with an accuracy of
greater than +/-2.5% (post-trimming). Typical oscillator frequency is 100MHz with
startup time of less than 5usec. Total power consumption of circuit is less than
50uA.Frequency peaking is < 5% (During startup). Highly insensitive to supply variation
and supply rejection of greater than 30 dB for all frequencies from 0 to 1GHz at 1.1V
supply. In normal mode output frequency is 100MHz and sleep mode is of 166KHz.
It consists of circuit which continuously monitors oscillator output frequency and triggers
an error signal when oscillator output frequency crosses +/- 10% of its nominal value.

5. 8-bit 50 MSPS Current Steering DAC :
Responsible for design of current steering DAC for video application. Designed the current
sources for DNL/INL of less than 1 LSB considering all non-idealities (mismatch, output
impedance and other systematic errors) and optimum switch sizes for less area and power
requirement of digital circuit. The segmented scheme has been used to have less DNL for
given area and power requirement. The top-level integration with Driver circuit is in
progress.

6. 1.6GHz 4-bit 100 MSPS Pipeline ADC For Sub-sampling Application (0.15um SOI
technology) : (Blocks : Sub-ADC and 2bit Flash )
Design, layout and characterization of Sub-ADC and 2bit flash ADC.
Circuit design of Sub-ADC and 2bit flash module in pipeline ADC for SOI technology at 100
MSPS for target offset of less than 9mV.

7. 1.6GHz 4-bit 100 MSPS Pipeline ADC For Sub-Sampling Application(0.18um CMOS):
Designed MDAC, Sub-ADC and 2-bit flash module in pipeline ADC for 180nm technology to
work at 100MHz for target offset. Designed non-overlapping clock-generator for 4-bit pipeline
ADC. Designed common mode buffer with common mode signal variation of less than 10mV in
worst conditions. Made layouts for these blocks with considerations of required guidelines
(matching, symmetry, parasitic delay, and parasitic sensitivity and EM checks). Post layout
simulation results across PVT conditions are within target specifications.

6. 8-bit 250 MSPS Pipeline ADC (0.18um CMOS) :
Designed S/H, Sub-ADC, flash adc and comparator for mixed mode sample and hold circuit
with low power architecture to meet target specifications of delay and input referred offset.
Made layouts for these blocks with considerations of required guidelines (matching,
symmetry, parasitic delay , parasitic sensitivity and EM checks). Design and layout of DC
blocks such as Voltage reference and common mode buffer. Post layout simulation results
across PVT conditions are within target specifications. Silicon results confirmed the DNL <
1LSB and INL < 2LSB.

7. Design and Layout for LVDS Transmitter(five channel) for 100MHz ADC
(0.18um) :
Responsible for circuit design, layout and characterization of LVDS Transmitter for
100MSPS ADC as per IEEE standard (General Purpose Link). The post-layout results
confirmed the target specification of skew (Tskew1 and Tskew2), output offset, rise-fall
time, output differential level across PVT conditions and other dc specifications. Did
layout with considerations of required guidelines (symmetry, matching and EM-checks).

7. Test plan for 8-bit 250 MSPS Pipeline ADC :
Responsible for preparing testplan (consisting test setup, test methodology with available
resources and test sequence) to validate 8 bit 250 MSPS pipeline-ADC.
Prepared the testplan for evaluating ADC static parameters (INL, DNL, offset error and
gain error) and dynamic parameters (SFDR, THD, SNR and SNDR). Also did automation
for post processing of ADC output data for evaluating these parameters.

8. Low Drop out Regulator (0.5um CMOS) :
Responsible for design of LDO to meet for target specifications of power consumption , load
regulation , line regulation and setting time. Performed a design of Low Drop out Regulator for
battery charger in 0.5-micron CMOS technology. Architecture was of series type load regulator
having PMOS pass element. The load current could vary from 100 uA to 500 mA with line and
load regulation of +/- 0.2% and settling time less than 2 usec and drop-out voltage of 0.5
volt and output of 4.5 volt.

9. Testing of Analog to Digital Converters :

Involved in developing test cases and program for static parameters (INL, DNL, GAIN and
OFFSET error) and dynamic parameters (SFDR, THD, SNDR, SNR) for ADC14155 and
ADC14156 with available test pattern. INL and DNL were verified using both ramp based and
sinusoidal based histogram method.

EDUCATION :

Final Year Thesis (M.tech): Design of Track and hold circuit for 10-Bit Pipeline
ADC, modeling and simulation of sampling noise in time domain.