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Hardware Intern Resume

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Objective: Solutions driven, enthusiastic and organized individual seeking Electrical Engineer position.

Skills:
HDL’S: Verilog, Verilog PLI, VHDL (novice), System Verilog.
CAD Tools: Altera (FPGA Design Tool and NIOS2), Xilinx ISE, Modelsim, Icarus Verilog, Cadence (Virtuoso Layout and Schematic Editors), VCS, Design Compiler.
Languages: C, C++, Assembly, VB, Basic Perl.
Operating Systems: UNIX, Linux, Windows XP, MAC
Development Board: CoolRunner CPLD of Xilinx, Cyclone FPGA Altera, ARM7
Instruments: Oscilloscope, Spectrum Analyzer, Network Analyzer

Education

  • M.S Electrical Engineering
  • B.S Electronics and Telecommunication

Experience
Confidential,Mountain View CA (Jun 10 –Dec 10)
Hardware Intern

  • Created and designed test set up for prototype boards.
  • Debugging, Validation and power analysis of HW prototype board.
  • Done characterization and validation of PIR sensor amplifier.
  • Burning firmware into hardware and closely work with software staff

Confidential,India (Jun 08- Dec 08)
Design Engineer in VLSI technology

  • Successfully integrated the hardware card of CNC machine into FPGA using Xilinx tool.

Confidential,India (Jun 07- Jun 08)
Graduate Trainee (R&D in Microwave and Optical Communication)

  • Developed a prototype design for Fine Pointing and Acquisition mechanism for free space optical link comprises of mixed signal circuitry and mechanical assembly.
  • Implemented I2C protocol for the design and done parallel and serial interfacing to get the data.
  • The whole circuitry designed using Orcad and got PCB fabricated.
  • Bring up the board and mount the components and validated the design using software.
  • Software was written in VB to control the whole system.

Confidential, (TA) (Feb 09- May 09)

  • Setup and documented wireless experiments using Trans receivers from Analog Devices

Academic Projects:
Developed Verilog Based Simulator for Network Simulator using CAD tools on Linux platform

  • Developed Verilog PLI for IEEE 802.3 100base Ethernet standard’s MII interface
  • Established MAC-Phy communications.
  • UNIX socket programming used with threading mechanism.
  • Wrote IEEE format report for the project done in team.

ADC validation using using FFT algorithm on ARM7TDMI RISC processor

  • Preprocessing circuit using op-amp was made on general purpose board for characterization.
  • Validation is done by interfacing preprocessing circuit with ARM board ADC and Matlab.
  • Software was written in embedded C

FFT algorithm designed in RTL, interfaced to embedded system made using SOPC builder

  • FFT code was simulated and synthesized using Quartus2 of Altera.
  • NIOS integrated development environment used to write C program.
  • Successfully implemented the hardware and software into FPGA board using Avalon interface.

Data unconfuser Engine designed to handle streaming data in RTL

    • Based on CRC type register, test bench provided 700bit key to unconfuse
    • Simulated using Modelsim simulator and synthesized using VCS and positive slack achieved.

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