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Senior Hardware Design Engineer Resume

Sunnyvale, CA

OBJECTIVE:
Senior Hardware Design Engineer

SUMMARY:
More than 10 years extensive hands-on experience in FPGA, board and system level hardware design. Experience with various platforms, working environments, languages and design tools.

  • Proven ability to provide new commercial product development from the architectural concept through the design to manufacturing within budget and on time.
  • Extensive experience in High-Speed Digital Design including high-speed backplanes.
  • Analog circuits design experience, including ADC/DAC and power supplies.
  • Experienced with several FPGA vendors tools and devices.
  • Supervised PCB layout and assembly.
  • Familiar with DFM and DFT process.
  • Supported operation with production boards, resolving design and production issues, which increased yield by 50%.
  • Exceptional hardware debugging and troubleshooting skills.
  • Hardworking, detail-oriented professional, positive attitude and desire to succeed.

TECHNICAL SKILLS:
Programming Languages: C/C++, VB, Asm x86, Asm 8051
Hardware Description Languages: Verilog, VHDL
FPGAs:Xilinx (Spartan 3, Virtex-II/ Pro, Virtex-4), Altera (Stratix GX), Lattice (LatticeSCM)
Synthesis / Verification: Synplify, ModelSim, Aldec Active HDL, Xilinx, Altera and Lattice design tools, MatLab
Schematic Capture / SI Tools: DxDesigner, OrCAD, Altium Designer, HyperLynx
Technologies, Protocols, and Interfaces: Ethernet 100/1G/10G/XAUI / RapidIO / ATM / SONET / POS-PHY / UTOPIA / T1 / E1 / T3 / TDM switching / FEC / HDLC / PCI / cPCI / PCIe / ATCA / StarFabric / DWDM / DDR/DDR2 / QDR / I2C / SPI / USB / GPIB / JTAG / RS-232
Microprocessors, Network Processors, DSPs: Broadcom BCM5662x, BCM5674/5695, Freescale 8548, 8560 (PowerQUICC III), 8280, 860, IBM PowerPC 750, TI DSP 320C62xx, Intel x86, 80x51
Equipment: High-Speed oscilloscopes, Logic analyzers, in-circuit emulators, JTAG debuggers, TDR, network / spectrum analyzers
Operating Systems: Windows, Linux, Unix

EXPERIENCE:
Confidential, Milpitas, CA 2010 - present
Sr. Hardware Engineer (contractor)

  • Performed EDVT and failure analysis of SSD drives. Participated in design of next generation SSD.

Confidential, Mountain View, CA 2007 - 2009
Sr. Hardware Design Engineer

Matisse Networks delivers optical burst switching system for metro networks.

  • Designed boards for a new fully redundant Telco grade Matisse platform.
  • Proposed architecture and designed application packet engine line card (BCM5662x). Evaluated Lattice FPGA implementation of SPI4.2 to XAUI/HiGig bridge.
  • Redesigned Optical amplifiers (EDFA) and optical power monitoring board.
  • Took ownership of all Matisse' production boards. Resolved various design and production issues.
  • Debugged and modified CPLDs and FPGAs for all production boards in the system.

Confidential, Mountain View, CA 2002 - 2007
Sr. Hardware Design Engineer

Catapult Communications is the leading provider of test systems for next generation digital telecommunications.

  • Designed and released for production multiprocessor boards for DCT2000 and M5000 platforms of the Catapult test systems (Freescale 8560/8540).
  • Designed cPCI multiprocessor card, utilizing high-speed serial Mesh interface and OC-3 /OC-12 optical link (MPC8280, IBM PowerPC750). Successfully resolved signal integrity and microprocessors chip-level issues.
  • Wrote and synthesized Verilog code for two million gate Xilinx FPGAs, implementing ATM cells switching, traffic monitoring, flow control management, CAM, support of various standard and proprietary interfaces.
  • Designed T1/E1, OC-3 and Ethernet physical interface cards. Developed FPGAs, supporting TDM switching and synchronization, implementing hash function, links monitoring and various diagnostics.
  • Designed boards for testing of the Mesh backplane and cPCI boards. Developed tests for JTAG boundary-scan of various production boards (Corelis).

Confidential, Sunnyvale, CA 2000 - 2002
Sr. Hardware Design Engineer

Spirent Communications is a global provider of testing solutions that enable the development and deployment of next-generation communication and networking technologies.

  • Proposed architecture for single-board T3 modem solution (672 V.90 channels), part of Zarak's bulk call simulator. Designed and released for production two DSP boards (TI 320C6203) for data/ fax modem and voice quality measurement.
  • Designed proprietary test board for DSP boards development. Participated in boards' troubleshooting software design.
  • Designed two FPGAs implementing several standard interfaces, TDM data switching and SS7 support.
  • Modified several CPLDs and FPGAs for production boards.

Confidential, Milpitas, CA 1995 - 2000
Senior Engineer

For this manufacturer of the disk drive subsystems designed digital and analog test equipment for analysis and testing of the magnetic heads and head stack assemblies (HSA).

  • Led Read-Rite HSA tester design team. Developed digital and analog boards for two generations of the tester. Provided hardware and software (VB) modifications of tester for Read-Rite HSA products.
  • Designed hardware, developed algorithms and implemented production tests for HSA preamplifier diagnostics, magnetic head reader / writer performance analysis, HSA assembly verification.
  • Designed and prototyped programmable narrow band-pass filter for spectrum analyzer
  • Evaluated, characterized and designed-in Magneto-Resistive and Thin-Film Pre-Amps chips. Interacted with the channel and pre-amp chips vendors for resolving specification and chip level issues.

EDUCATION:
Master of Science in Electrical Engineering (with Honors)

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