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Software Engineer Resume

Raleigh, NC

OBJECTIVE:
Seeking a full time position in the field of ASIC Design/Verification, Computer Architecture, VLSI.

EDUCATION:
Master of Science in Computer Engineering

Relevant Coursework: Computer Design and Technology, ASIC Design, ASIC Verification, VLSI System Design, Architecture of Parallel Computers, Computer Networks, DSP, Embedded Systems with Linux and Android, Managing Complex IT Systems

PROFESSIONAL EXPERIENCE:
December 2009-June 2010: Associate Software Engineer, Confidential

TECHNICAL SKILLS:
Languages: C, C++, Verilog, System Verilog, Perl, 8051/8085 Assembly Language Programming, VHDL, OpenMP.
Operating Systems: Linux, Windows.
Tools: HSpice, Modelsim, Synopsys Design Vision, Cadence Tool Suite (Virtuoso Schematic Editor, Virtuoso Layout Editor) ,Matlab, AVR Studio, Analog Artist.

PROJECTS:
COMPUTER ARCHITECTURE/CPU ARCHITECTURE

  • CACHE DESIGN, MEMORY HIERARCHY DESIGN: Designed a generic cache module that can be used at any level of memory hierarchy. The cache was configurable in terms of supporting any cache size, associativity and block size. Evaluated the simulator with SPEC address traces for gcc, perl,vortex, compress and go. Analyzed the trends in Miss Rates, Average Access Time (AAT), Energy Delay Product (EDP) for multiple configurations using PERL scripting.
  • BRANCH PREDICTOR: Designed a Brach Predictor that was configurable in terms of supporting any prediction algorithm such as Bimodal, G-share and Hybrid. Evaluated the simulator using SPEC address traces and analyzed the trends such as Number of Mispredictions and Misprediction-Rate.
  • TOMOSOLA'S OUT OF ORDER EXECUTION PIPELINE: Implemented Tomasulo's out of order execution pipeline for microprocessors in form of simulator and measured the performance for different scalar and superscalar designs in C.

VLSI DESIGN

  • Designed and simulated high speed 45nm, 64bit Content Addressable Memory (CAM) working at 1Ghz using Virtuoso Schematic and Layout Editor and performed the LVS and the DRC checks for the same. It had a 9T NOR type bit cell, Dynamic Decoder, Bit Line/Search-Line conditioning circuitry, Priority Encoder(Low), TSPC Registers.

ASIC DESIGN/VERIFICATION

  • Designed and developed a Layered and Object Oriented Testbench in System Verilog for the verification of the control, and data path of a PIPELINED LC-3 Microcontroller with a comprehensive instruction set.
  • Designed and implemented Viterbi Decoder that solves the Hidden Markov Model Problem using ModelSim for RTL and did Synthesis for the same using Synopsys Design Vision. Calculated the Area, Energy, Delay and generated Timing reports using the TCL scripts.
  • Designed a layered test bench capable of generating multiple constrained and randomized instructions and an interface to the DUT to verify various functionalities of a Basic ALU.
  • Designed and Synthesized a search engine where two string searches happen in parallel using Verilog HDL. The two strings to be searched were stored in the memory using memory generators.
  • Designed, Synthesized and Verified a module that accumulated statistics on an incoming data stream consisting of two individual bytes in Verilog HDL. The statistics accumulated were in terms Grey Code or Even Parity observed in individual bytes.

EMBEDDED SYSTEMS

  • Developed an application for an ARM microprocessor on a Beagle board for calculating the distance from an arbitrary position on the surface of the earth to the nearest monitoring station and evaluated the timing behavior for the same.
  • Performed the Analysis and Optimization of a JPEG Image Decompression. Gprof was used to gather timing information which was used along with Advanced SIMD instructions in optimizing the code.

PARALLEL PROGRAMMING

  • Cache Coherence Protocols Simulator (MSI/MESI/MOESI) implementation in C++. Analyzed the speed up obtained with respect to the different number of threads.
  • Open MP Parallel Programming: Parallelization of Diagonalization loop in Gauss Law, Parallelization of loop in Image Processing, Single/Doubly Link list Parallelization with implementation of user defined locks.

PAPER PRESENTATIONS AND PUBLICATIONS:

  • Presented a paper on 'Machine Vision' at VITALITY 2009 which was a technical event held at Vishwakarma Institute of Technology,Pune.
  • Presented a paper on 'Stereo Vision and Applications' at Credenz 2008 which was a technical event held at Pune Institute of Computer Technology,Pune.
  • http://www.eeweb.com/project/vinit_apte/depth-perception-using-stereo-vision

AWARDS APPRECIATIONS AND ACHIEVEMENTS:

  • Ranked ninth in University of Pune examination for year 2007-08.
  • Successfully completed Accenture's Greenfield Training in SAP-ABAP.

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