B.S. Electrical and Computer EngineeringProfile
- A highly accomplished ASIC layout engineer with extensive depth of knowledge into all facets of ASIC/VLSI integrated circuit design. Lead on approximately 60 IC's during my career. Some RF design experience.
- Analog CAD group manager while at Raytheon. Managed 8-10 layout people releasing 3 analog designs per week. Some Analog design experience.
- A proven project manager of multi-site international projects.
- An employee who has consistently earned the respect of his co-workers and peers.
- CAD Layout Group Manager. Arranged and set up preliminary, detailed and final design reviews for a GaAs Analog CAD group. Created all check off procedures to assure first pass design success (approx. 99% success rate). Final sign off responsibility on approximately 3 designs per week. Defined work allocation, schedules, priorities, meetings, and individual staff reviews.
- ASIC/VLSI Layout Engineer of numerous designs for sub micron VLSI Silicon CMOS process. Preformed custom, semi-custom and gate array layout using Cadence tools. Lead layout designer on approximately 60 IC's.
- Coordinated multi-site group whose purpose was to correct, facilitate and create an error free procedure for the mask release process from multiple design center locations. Error rate reduced by 60%.
- Software license database management. Compiled Excel spreadsheet that monitored all aspects of software licenses, i.e. cost, type, expiration date, location, etc. for numerous software vendors and design center locations.
Confidential, Sr. Applications Engineer 2007, Senior Applications Engineer. Customer service for all Simucad software products. Layout tools, RF Spice, IC Design tool suite.
Independent Contractor, IT system enhancements, Computer enhancement related issues, Microsoft tools instructor. PC repair technician. 2002-2006.
Confidential, Chelmsford Ma. Staff Design Engineer 1996-2002 Coordinated an international, interdepartmental team focused on the creation and improvement of a first pass success IC design release process, error rate reduced by approximately 60%. U.S. software vendor coordinator, maintained spreadsheet monitoring all software license issues, i.e. type, expiration date, function, cost, etc. (Hired by VLSI Technology 1996, bought out by Philips 1998)
Confidential, Andover Ma.1987-1993 CAD/CAE area 1st Shift Supervisor. Managed all aspects of integrated circuit design from netlist to delivery of mask sets. CMOS Silicon sub micron gate array layout ASIC engineer using Tangent for layout and Dracula for DRC and LVS. Developed numerous clock tree solutions on 25-65MHz designs. Layout and design of the three chips that control the guidance system of the PATRIOT missile system. Layout of numerous 160k gate array designs. Created foundations for 20K, 44K, 77K, 100K, and 171K, sub micron silicon gate arrays. Layout of chips in the Globalhawk and Predator drone surveillance systems.
Confidential, Andover Mass. 1984-1987 System supervisor CALMA graphics design system. Responsible for library management, chip layout and release to mask making. Created the foundation of several gate array families (3K, 5K, 10K, 15K, 1.25micron gate arrays). Responsible for the personalization of numerous gate arrays.
Confidential, Bedford Mass. 1979-1984 Engineer, Supervisor Computervision CADDS2 graphics design system (2-4 people). Layout of numerous custom and semi custom 2.0 and 5.0 micron CMOS silicon and CMOS/SOS circuits. Layout of numerous 2.0 and 5.0 micron library elements.System/Languages Experience CALMA, CADDS2, CADENCE tools, UNIX, LINUX, Solaris, Mentor Graphics tools, Excel, Power Point, FORTRAN, ISO9000 Auditor, C++, Some Verilog, HDL, VHDL Web Page Design, Avanti Tools, Microsoft tool suite. SIMUCAD tools.