Design Engineer Resume Fremont, CA - Hire IT People

EDUCATION

RELAVENT SKILLS

5.5 years of experience in logic design including synthesis, place and route, and timing closure and embedded design using soft-core microprocessor in Xilinx FPGA
Hardware design including schematic capture, board layout, and testing employing DFM, DFT and EMC techniques
Knowledge of various bus protocols including VME, I2C, SPI and OPB
Proficient in Verilog and VHDL coding, Xilinx ISE and EDK, Lattice ispLEVER, Modelsim
Working knowledge of C, PCad, Orcad and Specctra PCB tools, IC station and LEdit IC design tools
Advanced coursework in analog and RF circuits and IC manufacturing technology

PROFESSIONAL EXPERIENCE

Development Engineer, Confidential, California: May 2009 – Oct. 2011.

Led a team of engineers to design FPGA logic for a DNA sequencing instrument – Worked with SW engineers on interface definition and participated in a cross-functional system integration team to meet an aggressive schedule
Using VHDL coding platform, designed logic for motor drives, illumination control, flow-rate measurement, remote programming, data storage, and system status monitoring
Worked on FPGA design for a motor-control module for driving stepper motors with encoder feedback and DC motors with optical sensors
Participated in a team to design logic for data transfer and storage in SRAM memory and image data analysis using Spartan 6 FPGA
Participated in system architecture, design reviews and FMEAs in ISO 13485 and FDA regulated environment

Design Engineer, Confidential, Cleveland, Ohio: Oct 2006 – May 2009.

Designed logic for a 200 MHz Digital Signal Oscilloscope with variable sampling rate and configurable memory buffer for use in defense application
Executed complete design cycle including specification generation, circuit design, PCB layout, logic development, testing, and transfer to production for modules used for digital I/O and pattern generation
Implemented VME bus interface in Xilinx FPGA using Verilog for benchmarking data rate of a VXI-LXI Gigabit Ethernet Slot 0 card
Troubleshot critical logic design issues in timing module for LXI compliance and floating point data analysis module for a temperature and voltage measurement device using Modelsim and Chipscope
Led a cross-functional team spread over locations in US and India to address part obsolescence issue by researching potential solutions and performing cost-benefit analysis and project management activities to meet tight schedule
Participated in conceptualization and implementation of a high-speed LVDS proprietary bus architecture for module interconnectivity in Lattice FPGA
Worked with vendors and FAEs for component selection, generated BOM and ECO, documented technical specifications, work instructions, and test results

ADDITIONAL INFORMATION