Sr. Design Engineer Resume Dallas, Texas - Hire IT People

Senior integrated circuit design engineer

SRAM cell designs and layout for embedded SRAM and FLASH memory circuits used in high-end processors and wireless applications.
Physical implementation from circuit schematics to chip layout including chip floor planning, cell placement, and parasitic extractions for SDA memories with DFM implementation.
Custom Integrated Circuit design and layout using Cadence Virtuoso®, Mentor Graphics®, IC Station® and ,Calibre® / Hercules® for verification using scripts and Perl codings.
Understanding of deep sub-micron CMOS, design, processes and Optical Proximity Correction (OPC).
Fluent in Japanese (native).

PROFESSIONAL EXPERIENCE

Confidential - Dallas, Texas (Contract) 4/2010 ~ 10/2010
Sr. Design Engineer - Confidential

Participated in the redesign of a flash memory circuit for hand-held consumer applications, utilizing ultra low power CMOS technology in a 65nm Process.

Confidential -San Jose, California 2008 ~ 2009
Sr. Design Engineer,Confidential

Generated test structures for characterization vehicles based on alliance partners’ SRAM cell designs at 45nm, 40nm; including 32nm CMOS and SOI processes to assist production ramp-up and yield improvement activities. Alliance partners were IBM, Toshiba, and Samsung Electronics. Mentored colleagues in cell design and its process sensitivities relative to for the yield analysis.

Confidential - Dallas, Texas 1998 ~ 2007
Design Engineer, Confidential

Supported design and development of the 32nm process node SRAM cells for foundries.
Co-developed, delivered and fanned out High Density and High Performance SRAM cells for production at 45nm to 125nm lithography process nodes for both internal and external customers as well as for foundry wafer fabs.
Co-developed OPC and SRAF (Sub-Resolution Assist Features for the masks) with Resolution Enhancement Technology Team, production release and yield improvement on various types of SRAM cells for customers using 180, 125, 90, 65nm lithography nodes.
Established the methodology for automatically extracting and installing OPC features and SRAF generated by the RET Team into the complete cell arrays with the core-bit cells and infrastructure cells that are used for the product design of the SRAM macros. This procedure immensely improved the cycle time of the OPC development to the Bitcell PDK (Process Design Kit) upload operations for the tape-out and the fan out.

Confidential - Dallas, Texas 1991 ~ 1998
Design Engineer, Confidential

Design lead of the 512K and the 2Meg SRAM designs for the statistical defect analysis (SDA) and for design for manufacturability (DFM) purposes. These included circuit simulations and the physical implementation from circuit schematics to chip layout, floor planning, cell placement, and parasitic extractions. These designs contributed to the SRAM testing and yield enhancement teams for internal and external customer products.
Co-developed, delivered and fanned out various SRAM cells using 0.5-micron CMOS process / harmonized process technologies (DRAM and Logic) for Sun SPARC and TI chips.

Performed cell stability simulations for DC noise margin, single event upset (SEU), and performance with SPICE.

Confidential - Dallas, Texas 1980 ~ 1991
Design, Product Engineer, Confidential

Co-developed and characterized first 4T-2R 28um² SRAM cell, using a 1-Meg SRAM design with 0.8um process technology, using a test vehicle at the research lab (SPDC).
Designed and released to production a 1-micron CMOS (ACL Family), and Advanced Low Power Schottky Transistor (ALS Family) of standard logic products. Provided production support, and served as the technical/production staff at TI Japan.
Improved multi-probe yields on Canon camera devices using IIL (Integrated Injection Logic bipolar) process.
Technical interface between Dallas, Taiwan, Japan, and customer (Canon) in Japan while coordinating and sustaining high volume production.

EDUCATION

BSEE Michigan Technological