Project Based Intern Resume

SUMMARY

Graduate student seeking Opportunities in teh area of Electrical engineering with focus on ASIC design, Mixed Signal IC Design and Physical design.

TECHNICAL SKILLS

ASIC Design
Mixed signal IC design
FPGA (SOC) prototyping.
Embedded System Design
C, C++, Python
Scripting: shell
ATPG using TetraMAX
MATLAB, LabView
HDL: Verilog, System Verilog.
Cadence Tools: Virtuoso, composer schematic.
Synopsys Tools: Design Vision, Prime Time, IC Compiler, Library Compiler, Wave View

PROFESSIONAL EXPERIENCE

Project Based Intern

Responsibilities:

My role in teh research work done is to study “Bipolar Charge - Plasma transistors (BCPT)”, analyse their drawbacks, find ways to overcome them and improve teh overall performance of teh BCPT.
New symmetric device proposed in teh paper outperforms teh conventional counterpart BCPT in all aspects like current gain, frequency of operation, etc.

Environment: Silvaco Atlas and TonyPlot, Linux Red-hat.

Publications: J. R. Veluru, L. K. Bramhane, N. Upadhyay and J. Singh, "Symmetric bipolar charge-plasma transistor with extruded base for enhanced performance" in Electronics Letters, vol. 51, no. 13, pp. 1027-1029.

Academic Projects

ASIC Design of Low Power Mini Stereo Digital Audio Processor

Responsibilities:

Designed an ASIC chip to implement Digital FIR filter capable of performing audio processing functions.
RTL codes and test bench setup, written in Verilog and final gate-level netlist was obtained using Design Compiler.
Automatic placement and routing is done using IC compiler.
Power and timing analysis was done using Design Compiler.

Environment: C++, Verilog, ModelSim, IC Complier, Design Compiler.

Design of an operational amplifier

Responsibilities:

Designed a differential-input single-ended output two-stage amplifier satisfying all teh specification mentioned without using any ideal current source.
Instead of ideal current source Self-biased current source with startup is used.

Environment: Cadence Composer-Schematic, HSPICE.

Microprocessor Design

Responsibilities:

Designed a fully functional 16-bit Overlay Microprocessor and Implemented teh design on FPGA board (ZYNQ - 7000 SOC).
RTL code and test bench for testing teh behavioural simulation of teh code are written in Verilog.
Main feature of design is Instruction set dat operates on customizable functional block whose working can be specified by teh user. Instructions are entered into teh instruction space using external keyboard.
Final implemented design was tested using some random Test vectors.

Environment: ZYBO board (ZYNQ-7000 SOC), Xilinx Vivado and ISE, Keyboard to ZYBO PS2 interface, ZYBO to VGA.

Trivium Cipher design and simulation

Responsibilities:

Designed Trivium Cipher (a linear shift register based cipher) using IBM 130nm technology.
Started from designing basic building blocks (Flipflops, XOR and AND gates) and manually routing them to complete teh Trivium Cipher. DRC, LVS, & QRC were done using Cadence Virtuoso layout editor and composer schematic.
Static timing analysis is performed using Synopsys Prime Time and Circuit is designed in a way to optimise power.

Environment: Cadence composer schematic, cadence virtuoso layout editor, HSPICE, Wave view, Prime time and Shell scripting.

Fault Detection, Simulation and Sampling of implemented Combinational Circuits

Responsibilities:

Implemented combinational and sequential circuits at gate level using Verilog.
Detected Collapsed stuck-at-faults. Test vectors and fault coverage was found using TetraMAX tool
Demonstrated fault simulation using Parallel, Deductive, Concurrent fault simulation and Critical path tracing methods
Test pattern is generated for Built-In self-test(BIST), Boundary Scan and different scans are dealt.

Environment: TetraMAX, Design Vision.

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