Graduate Research Assistant Resume

SUMMARY

Extensive experience in Verification using System Verilog, UVM of Complex Designs, Python, DFT
Completed 3 ASIC projects using Synopsys ICC
Experience in Block level place and routing
Experience of 2 years in doing Research, developing RTL code in Verilog and verification using SystemVerilog
Designed a Video Motion Estimator chip using Verilog and verification using Systemverilog, UVM, writing random stimulus testbench, got 100% Functional Coverage
Experienced in Static Timing Analysis using Synopsys VCS(Primetime) tool
Experience in writing Assertion based test bench and getting 100% Functional Coverage
Experience in Low Power Analysis of SRAM Cell using Low power Design
Proficient in writing Test bench using System verilog including Monitor, Scoreboard, Generator, Self - Checker.
Experienced in ASIC flow design, UPF, scripting languages like Python, C
Experienced in designing of SRAM under various constraints including low power dissipation and using HSPICE for simulation and circuit analysis.
Experience in designing Schematic and Layout of circuit and using different techniques such as DRC, LVS and extracting parasites.

TECHNICAL SKILLS

High Level Languages: C/C++, Verilog, Systemverilog, UVM, Python, TCL

Software Platform -: OpenCL, OpenGL

Operating Systems: , Red Hat Linux, Mac OS X El Capitan, Windows

Computer Architecture: MIPS/RISC Microprocessor, Parallelism, GPU Architecture, Memory Hierarchy, Pipelining, AMBA bus, AHB . DMA bus, DDR3,PCI-Express

Scripting Languages: Perl basics, Shell Scripting, Unix

Lab Equipment: Lab view, Multimeters, FPGA, ARM Cortex Microprocessors

Communication Skills: Bilingual English/Hindi, Excellent verbal and oral communication skills. Excellent leadership, team work and time management qualities enhanced by group projects and extra curriculum activities

PROFESSIONAL EXPERIENCE

Graduate Research Assistant

Confidential

Responsibilities:

There are various blocks of SVVM (System Verilog Verification Environment) such as BFM, Monitor, Driver, and Checker that were implemented.
A complex Scoreboard was written and designed was verified by running for 1000 cycles in self checking.
The Preliminary functionality of DUT was verified by writing corner and special cases in Test Bench
Implemented all blocks of SVVM, and also complete Functional Coverage measurement including stimulus condition and device response.
Physical design including Floor plan, power grid analysis, placement, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity.
Scoreboard, Driver, Monitor, checker were implemented for VE.
Test cases were written applying Random Stimulus to verify the expected output from the DUT
Designed a motion Estimator using Verilog and created DV using Systemverilog
Did Static Timing Analysis and debugged Setup and hold time violations
Floor planning, Routing, placement and Pre silicon validation using Synopsys Tools
Build complete verification environment including checker, scoreboard, generator, driver
Implemented project in ARM microcontroller
Successfully controlled the appliances of house using cellular phone
Project was best in the class
Using industry tools, designed smallest area SRAM cell
Designed circuit using 6T Transistors
Created custom layout for 6T SRAM cell
Created DV including checker, scoreboard, self checking

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