Staff. ASIC Design Engineer Resume

SUMMARY

Electrical Engineer offering research and engineering design experience for ASIC/DSP as hands - on design.
Ability of ASIC Modem design efforts for global leaders in communications product development.
Expertise implementing digital signals and communication algorithms.
Verilog-HDL, Synthesis(Design Compiler/RTL Compiler/FPGA)
CDC Analysis/Static Timing Analysis
System-Verilog/Specman(OVM, Intermediate level)
Hands-on experience of DSP Algorithm (C-language/Matlab)
Knowledge on Communication System Architecture
Knowledge on Formal Verification, Power Gating, DFT/ATPG
Tcl, C-language/Digital Signals Processor

PROFESSIONAL EXPERIENCE

Confidential

Staff. ASIC Design Engineer

Responsibilities:

Contributed to develop IOT SoC
IOT SoC Project: Design interface for analog comparator, ADC interface for sensor subsystem, GPIO-mux, IO-padring
Contributed to develop LTE IOT modem by designing DSP blocks and testbench for test-automation wif Tcl/Verilog and its FPGA implementation
LTE IOT Modem ASIC Project: Designed Cell searching module(PSS/SSS), CFO estimation, fractional decimator/interpolator, digital signal processing modules by using Verilog-hdl

Confidential,

Sr. ASIC Design Engineer -

Responsibilities:

f receiver and transmitter(Rx/Tx) and structure/RTL design for supporting high-speed signal processing.
Validated performance and functionality by using Specman, Tcl, C-language/MATLAB, CDC, Static Timing Analysis (STA)
Receiver ASIC Project: Designed Halfband-Decimation filter. Validated performance and functionality using Specman(designing bfm/monitor/checker), Verilog-hdl and MATLAB/Tcl/C-language.
Transmitter ASIC Project: Designed Lagrange decimator, FIR filter wif parallel structure to process high-speed data rate(supporting 8GHz sampling rate) and SPI bus controller for flash memory.

Confidential

Sr. ASIC/DSP Design Engineer

Responsibilities:

Engaged in Structural design for LTE Modem and WCDMA., Collaborate wif strategic decision makers, and interdisciplinary engineering groups to design Modem ASIC. Identify and integrate opportunities to improve product performance into future designs.
Designed LTE/WCDMA Modem by using Verilog-hdl.
Validated performance and functionality by using System-verilog(OVM, DIP-C), Tcl, C-language/MATLAB, CDC, Static Timing Analysis (STA).
LTE Base Station Modem Design: Structural top-module ASIC design for Uplink/Downlink physical layer. Designed scalable IDFT for PUSCH demodulation, AGC/RSSI/7.5 kHz shifter, and FFT/IFFT by using Verilog-hdl.
WCDMA (HSPA+) Commercial Base Station Modem ASIC Project: Designed modem structure including reset/clock-domain scheme. Designed Advanced Receiver, FDE(Frequency Domain Equalizer), Support algorithm design FFT/IFFT algorithm by using C-language/Matlab and implemented by using Verilog-hdl.
WCDMA (HSUPA/HSDPA) Commercial Base Station Modem ASIC Project: Designed rake receiver and Digital Down Converter/Digital Up Converter (DDC/DUC). Successfully demonstrated and implemented ASIC for WCDMA and LTE modem for key partners KTF and SK Telecom.
Designed and developed wireless communications products as a part of engineering R&D efforts.
Successfully demonstrated and implemented ASIC for WCDMA for key partners KTF.

TECHNICAL SKILLS

Platforms: Linux, MS Windows, UNIX

Engineering Tools: Code Composer (TI DSP), DC Compiler, Conformal/Formality, MATLAB/Simulink, NC-Verilog, Prime Time, SPW, VCS, Specman/System-verilog, FPGA (Xilinx/Altera)

Languages: C-language, Tcl, Verilog-HDL, System Verilog, Specman/e-language

Hardware: WCDMA modems, LTE modems, ASIC

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