Senior RTL Design Engineer Resume Hillsboro Oregon - Hire IT People

SUMMARY

Independent, dependable, efficient and diligent technology leader wif significant experience in successful digital IC design. Design implementation includes full custom silicon, ASIC and FPGA in fast - paced, high-pressure, and intellectually challenging environments. Able to work cross-functionally wif all levels of an organization to manage timing, reliability, testability, and power to deliver a world-class customer experience.Core Competencies
Chip Definition Creation of design environment CAD/ methodology development Microarchitecture definition Logic validation Circuit design Schematic entry Synthesis, test suite and testbench creation Static timing analysis Silicon debug in lab Verification in system environment Transfer into production

TECHNICAL SKILLS

Program in C, AWK, TCL, Perl, Verilog, and UNIX csh.
Extensive use and debug of design tools and scripts including interfacing to tool vendor or design house.
Experience wif tools from Synplicity, Xilinx, Synopsys, Mentor Graphics, and Cadence including Synplify Pro, PrimeTime, VCS, Modelsim, and Stratus (HLS).

PROFESSIONAL EXPERIENCE

Confidential, Hillsboro Oregon

Senior RTL Design Engineer

Responsibilities:

RTL design of 2+ blocks on fully functional Astep.
Bstep for power reduction.
Assessed, and refined three original blocks, plus designed RTL of new block for Bstep.
Fully functional Bstep, RS400 obtained PRQ (Production Release Qualification).
Responsible for RTL design of 2 blocks in IVCAM MC A0 project.
Participated in bring up that showed functional silicon.
Responsible for RTL design of 3 blocks in IVCAM MA A0 project.
One block had no verification bugs.

Confidential

Delivered high standards

Responsibilities:

Confidential

Responsibilities:

Design creation, before RTL, schematics were used after a methodology was created.
Design verification done by verification of another designer’s block. (no separate verification group)
Package design.
Used leading edge tools, in some cases had to debug tool wif vendor.
Developed in house tools to completed design work.
Limited back end tasks, synthesis and timing analysis.
Developed testing and sort vectors.
Debug silicon in lab.
Transferred working silicon to production.