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Design Verification Engineer Resume

San Jose, CA


  • Graduate with a passion to create innovative systems, with strong hands on experience on engineering design tools like Synopsis VCS, NC - Verilog, Modelsim, Altera Quartus and languages like System Verilog, UVM/OVM, System Verilog Assertions and VHDL.
  • Three years of computer architecture research experience and extensive C/C++ experience and one year of design verification and ASIC experience.
  • Possess excellent scripting skills using Python/Perl. Proficient in various bus protocols like I3C, I2C, PCIe, UART, DPHY, CPHY and in Linux/Unix environment. Certified C, C++ and Java programmer. Proficient in Computer Architecture, Embedded Systems, Digital Design & Design Verification. Possess excellent communication skills, ability to learn and to work under any new concepts/environments and skilled to finish tasks in time. Team oriented and results driven.


Languages: System Verilog, VHDL, UVM/OVM, C, C++, C#, CUDA, Java

Scripts: Python, SQL database, T-SQL, HTML, Java Script, Perl script, Shell

Operating System: Linux Ubuntu 16.04, Linux Fedora, Sun Solaris, Windows 8, GNU compiler


Networking Protocols: TCP/IP, UART, I2C, I3C, DPHY, eMMC

Tools: NC-Verilog, Synopsis VCS, MATLAB, Simulink, NI-Labview, PSpice


Confidential, San Jose, CA

Design Verification Engineer


  • Implemented test logic and performed verification for I3C interface in Linux environment
  • Developed verification plans using UVM/OVM concepts and writing UVM sequences
  • Automated hardware testing process using Python script
  • Developeddesign verification for several high speed configurable bus designs
  • Worked on I3C, I2C, UART bus protocols
  • Developed I3C driver, scoreboards and checkers for verification
  • Handled scripting using Perl/Python for testing hardware components
  • Worked on Functional verification using eMMC and DPHY test chips
  • Developed I3C driver, handled System Verilog assertions, code coverage, scoreboards and checkers for master and slave using System Verilog
  • Debugging and testing of drivers, monitors, scoreboards, code coverage assertions, simulations and regressions

Confidential . Milpitas, CA


  • Developed test cases and test benches to validate teh design
  • Develop and debug teh communications between core and teh root complex
  • RTL modelling of network interface
  • Worked on various IP verifications and digital blocks at teh physical layer
  • Developing UVM sequences, constraint-random testcases, drivers, monitors, scoreboard, simulations, regression, debug, bug reporting/tracking etc …
  • Developed IP Pattern Generation & Simulation, RTL simulations and testing
  • Worked on IP Test Connectivity and Simulation debug
  • Worked on Digital IP verification using constraint-random coverage methodologies

Confidential, CO

Graduate Research Assistant

Environment: C, C++, Verilog, UVM/OVM, System Verilog, Perl Script, CUDA, Linux


  • Used C and C++ to implement high performance optimized stencil codes on multicore machines under GNU compiler
  • They are implemented on Linux OS
  • Design and architecture of application specific accelerators for stencil computations
  • Worked on parallel hardware/multicore architectures validation using UVM/OVM
  • Improved processor performance by 3x, Reduced Bandwidth, area and power by up to 50%
  • Implemented on Cyclone V FPGA using System Verilog, NVIDIA GPUs using CUDA and intel Xeon CPUs
  • Responsible for building teh most optimal parallel implementation of stencil computations on FPGA’s using System Verilog
  • Worked on optimizing teh Cache coherence operations
  • Extensively worked on Program transformations like Tiling, Skewing, Scheduling and Processor Allocation
  • Analyzed power data and optimized various architecture features
  • Developed Stencil kernels and benchmarks using GPU programming like CUDA
  • Worked with polyhedral compilation and polyhedral compilers. It uses programs involving nested loops and arrays represented as polyhedral
  • Solely responsible for implementing teh algorithm on FPGA’s and simulate parallel hardware
  • Developed test benches to verify teh functionality of teh design
  • Developed Optimal architecture design of various stencil operations like Gauss Seidel, Jacobi and Wave-2D and implemented them on FPGA’s towards hardware implementation and C, C++ and CUDA towards Software implementation under Linux environment


Digital Filter for Magnetometer Data

Environment: C, C++, MATLAB, Linux


  • Designed and installed a digital filter for Magnetometer Data from a satellite
  • Teh Satellite sends data to teh base station which contains lots of noise
  • Teh filter is designed using MATLAB
  • Developed C++ programs dat interfaced MATLAB code with teh workstation
  • Teh design module was added to teh backend of teh satellite mainframe
  • Performed shape specific Image Segmentation using matlab for Image Processing Lab at Indian institute of Science
  • Teh input was a set of images captured using digital camera and these images were processed to detect objects and find blood clots
  • Teh medical imaging project was performed using MATLAB using contour detection.
  • We also implemented teh project in C++ under Sun Solaris environment

Student Trainee


Environment: TCP/IP Manager, Networking, Navigation tools


  • Worked on Airport Communication, Networking and Navigation equipment’s in teh airport
  • Worked on debugging Networks and encoding and decoding of communication signals
  • Worked on arrangement, installations and repair of Networking and Transmitting/Receiving Antenna equipment
  • Worked on networking and communication equipment dat are used in Trains
  • Worked on maintenance of communication equipment in teh station
  • Worked on fixing network issues and antenna equipment
  • Used TCP/IP protocols to handle communication between various modules
  • Worked on debugging networks, implementing networking protocols and testing

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