SUMMARY:

• Computer and software engineer with 15+ years of experience delivering leading - edge processor, platform, software, and related technologies.
• A highly experienced technical program manager. Successfully leads technical and cross-group product design teams, managing software engineering teams, and mentoring junior engineers.
• Productively employs agile development methodologies.
• Expert in object-oriented design and programming (C++, C#, Java, Python) with extensive breadth and depth of knowledge and experience with the ability to rapidly assimilate new technologies.

TECHNICAL SKILLS:

Applications: Microsoft Excel, Outlook, PowerPoint, Project, Word, Visio; Adobe Acrobat, FrameMaker, InDesign; TeX, LaTeX, ConTeXt, LuaTeX, XeTeX; Bitkeeper, CVS, Git, Perforce Helix, Subversion

Languages: GNU C/C++, Visual C/C++, C#, Objective C, Java, IA-32 assembler, SQL, Flex, Bison, Scheme, Racket, Guile, Common Lisp, CLOS, Lua, Perl, Python, Haskell, Ada, GNU Make, CMake

Operating Systems: GNU/Linux (Fedora, Debian, openSuSE), Windows (Home, Pro, Server), Android, FreeBSD, IA-SPOX, VxWorks

Technologies: Intel IA-32 and Intel64 Instruction Set Architecture, Intel Software Guard Extensions (SGX), Intel Virtualization Technology (VT), Windows Driver Model (WDM), Windows User Mode Driver Framework (UMDF), Windows Kernel Mode Driver Framework (KMDF), Windows Biometric System (WBS), Qt5 Application Framework, C++ Standard Template Library (STL), Boost C++ Framework, .NET/Mono, LLVM, XML, JSON, AES, Elliptic Curve Cryptography (ECC), ECDSA, Public Key Cryptography, DSA, Cryptography for Intel Performance Primitives (IPP), PEM, base64, SPI, I2C, USB, Intel Platform Innovation Framework for EFI ( Tiano ), Extensible Firmware Interface (EFI), UPnP, TCP/IP, Component Object Model (COM)

PROFESSIONAL EXPERIENCE:

Confidential, Hillsboro, OR

Senior Staff Software Engineer and Security Architect

Responsibilities:

• Delivered an integrated fingerprint solution that reduced cost by $2 using a bare SPI sensor without compromising security.
• Successfully drove alignment of all teams when the change control board suspended the project due to one required team not being committed as the solution required connecting the sensor to a controller that violated current specifications.
• Delivered an architecture and prototype to control any SPI device securely from a software enclave. Being a generic solution, no additional effort would be required by Intel for a vendor to connect their device.
• Delivered security components for Intel True Key and Authenticate using Intel SGX technology for voice recognition, face recognition, and client-to-server communication that greatly increased security over existing software solutions but at a significate cost savings because it didn’t require additional hardware. Delivered a test framework and UI using C++ .NET and the Boost Unit Test Framework for initial product testing.
• Delivered a demo application using C++/QT5 that demonstrated a proposal for hardware encrypted video input to further harden facial recognition where the images and templates could not be accessed outside the secure enclave.

Senior Staff Software Engineer

Responsibilities:

• Drove the standardization of the micro-assembly language across Intel. The language had drifted with each product team, greatly increasing the support costs for the microcode tools team. Authored a standard specification, drove buy-in, and created an LL(*) parser with a tool to enforce syntactical compliance for all teams which reduced support costs and defects by over 80%.
• Defined and delivered an enhanced micro-assembler configuration language and a LALR(1) parser to allow project teams to handle more advanced microcode encoding situations without changes to the core micro-assembler, cutting changes to the core by over 50%.
• Delivered a LALR(1) parser for the next-generation architecture simulator allowing the architectural specification to be written in a high-level language and compiled into the simulator, breaking the final barrier preventing this project from success and allowing microprocessor architects to write the specification of instructions themselves and immediately use them in the simulator, resulting in better specification and earlier validation.

Platform Architect

Responsibilities:

• Defined and delivered the microcode for a new post-silicon validation tool that allowed collection of performance counters over multiple tests without modification of any test content, allowing for visibility not obtainable before, which helped increase memory bandwidth tests go from 20% utilization to over 90%.
• Delivered a Linux scheduler simulator that allowed for rapid scheduler research on highly-asymmetric platforms by extracting just the scheduler to run as part of the simulator, resulting in one patent filing and four papers accepted for presentation at real-time OS conferences.

Senior Staff Research Scientist

Responsibilities:

• Authored the architecture specification for the next-generation microcode patch format to allow for additional platform microcode and firmware to be delivered in addition to the microcode patch with 100% backward compatibility and be loaded securely.
• Delivered the next-generation microcode path tool written in Python which assembled all the various parts of the microcode patch correctly allowing for easy automation of creation of the patch to be signed.
• Designed and delivered an emulator for developing and exploring platform firmware and microcode extensions years ahead of first silicon. Supported both Python and Guile as extension languages and a significant portion (> 1/3) of the emulator was written in Python, allowing for easier customization and less changes to the core (written in C++) emulator.

Staff Network Software Engineer

Responsibilities:

• Defined and delivered pre-emptive thread scheduler and interrupt support for the EFI pre-boot environment which delivered more than double the network performance at 90% less CPU utilization while running multiple EFI applications concurrently.
• Led a team of 5 to virtualize the Intel/DEC 21140 and the Intel 82544 network interfaces to measure their performance under virtualization, providing recommendations on virtualization to the network product teams.

Software Engineering Manager

Responsibilities:

• Defined and delivered the first UPnP stack for Linux, first open sourced in August 2000, which became the standard UPnP stack for most UPnP devices.
• Delivered the first UPnP device to obtain an office UPnP logo, an Internet Gateway Device, which became a standard part of Intel’s home network gateway products.
• Delivered a reference UPnP Media server for an external software partner and an embedded, Linux-based UPnP Media Renderer device to the Intel ViiV product team.