- Senior Level Engineering Professional with a broad technical background and extensive experience in all phases of the product design - cycle from conception to production.
- Major strengths in Hardware Design and Development with emphasis in digital logic synthesis, implementation and verification.
- Concentration working in electronics industries focused in broadband delivery of audio, video, and data services in analog and digital communications.
CAD and PCB: Cadence/OrCAD/Allegro, Altium, Mentor/PADS/Xpedition/DxDesigner, AutoCAD/EAGLE
Simulation: Matlab, MathCad, PSpice, NI/LabView/Multisim, ModelSim, VisualDSP++. Code Composer
Logic EDA: Altera/Quartus, Xilinx/ISE/Vivado, Lattice/Diamond/isp, Cypress, Atmel, Mentor Graphics, Synopsys
Languages: C/C++/C#, Java, Visual BASIC, VHSIC/VHDL, Assembly Languages, Verilog, ABEL, AHDL
Processors/Cores: ARM, MIPS, PowerPC, x86, Blackfin/DSP, TMS320, PIC/PIC32, MSP430, AVR, PSoC, NIOS, Blaze
Confidential,Sandy Springs, Georgia
Senior Electrical Engineer
- Performed Research and Development in a multi-discipline team on new product concept requiring an ARM Cortex-M with DSP in firmware operating ‘bare metal’ without an OS with multiple motor control, front panel UI, music/sound playback and more.
- Responsibilities included firmware ‘ownership’ position with almost complete autonomy including code adaptation/modification decisions supporting both ARM and PSoC controllers for various prototype features like motors/drives, motion/speed sensing.
- Managed EMI/EMC emissions compliance including validating previous failed ODM results, identifying sources of failure, applying mitigation measures, verifying passing results, updating Mentor/PADS/DxDesigner schematic, layout and BOM.
Electrical Engineer / System EngineerResponsibilities:
- Developed and supported physically and behaviorally realistic simulated weapons and associated support systems for use in virtualized training environments. Contributed to successful government acceptance of U.S. Army Engagement Skills Trainer II (ESTII) system and U.S. Marine Corps Indoor Simulated Marksmanship Trainer (ISMT) programs.
- Optimized system and weapons accuracies exceeding customer requirements. Analyzed competitors system performance capabilities and design limitations. Designed weapon control and interface hardware. Developed ARM Cortex NXP/LPC/Kinetis firmware for live fire system hit detection. Developed embedded weapon firmware using IAR tools. Supported development of both BlueFire Bluetooth wireless and traditional tethered weapons.
- Managed ISMT system EMI/EMC emissions compliance including failed results sources and mitigation measures. Identified design oversights causing emissions failures; implemented successful system changes. Created and executed Jama test plans and procedures validating system and customer requirements and augmenting hardware/software integration/testing. Utilized Jira for problem tracking and implementing issue resolutions. Applied INCOSE engineering life-cycle V-model.
Product Development Electrical EngineerResponsibilities:
- Designed circuits and developed Microchip/PIC embedded firmware for real-time operation in limited architecture for solenoid pump operation with line-cycle voltage/current sensed power/speed control and continuous operation across wide AC voltage range below 120VAC to above 240VAC incorporating 'float-less' water level detection/sensing with activation of relay circuit interruption.
- Supported product BOMs including component selection/approval. PWB/PCB design, layout, prototype construction and testing. Performed product failure analysis with firmware only solutions saving cost of scrapping pre-built materials.
Senior Electrical EngineerResponsibilities:
- Designed and Prototyped PCI-Express (PCIE) multi-card optical interrogator based on Xilinx/Spartan6 FPGA supporting KHz scan rates with logic based peak detection/tracking, sub-picometer accuracy and repeatability with NIST-traceability, providing the full spectrum output of static instrument with the speed and range of a dynamic instrument, incorporating Double-Data-Rate3 Memory (DDR3) buffering, requiring synchronized precision quad channel 80 MSPS Analog-to-Digital Convertors (ADC) needing mid-femtosecond sampling clock jitter with Low Voltage Differential Signaling (LVDS) outputs.
- Recovered and Continued Hardware/Firmware Development of Optical Coherence Tomography (OCT) platform. A compact device controlled by a Microchip/PIC32 using an Altera/ArriaGX FPGA built with Quartus/DSP Builder, integrating swept fiber optic laser source, optical receiver, data acquisition and signal processing and real-time streaming over Giga-Ethernet.
- Identified failure root causes, implemented improved manufacturing processes with BOM changes for systemic RMA issues.
- Supported and maintained sm125/225 static and sm130/sm230 dynamic optical sensing interrogators and the ATE fixtures for component products. Support included NEBS GR-63/Telcordia compliance and MIL-STD-202G environmental testing.
Senior Hardware Engineer / Member Technical StaffResponsibilities:
- FPGA: Altera/NIOS secure virtual processor with customized architecture. Coded firmware for cryptographic operations.
- Specified interface FPGA for Broadcom back-end to CableCARD in first production (OCAP) host. Mitigated cryptographic Triple Data Encryption Standard (3DES) ambiguity in first generation back-end CableCARD interface.
- Field Programmable Gate Array (FPGA): CableCARD Interface; Altera/Cyclone with VHDL in Quartus integrating Verilog and Register Transfer Level (RTL) Intellectual Property (IP) blocks. Functional, drop-in replacement for MediaCipher embedded security Application Specific Integrated Circuit (ASIC) when paired with Multi-Stream CableCARD (M-Card).
- Identified ASIC bridge Dynamic Random Access Memory (DRAM) interface controller state sequence error causing random intermittent software failures, saved significant cost of replacing core ASTB design and existing platform software base.
- Extended architecture in DVi5000 ASTB while constrained to existing FPGA hardware; Cypress/Warp extreme utilization. Mitigated critical documentation over-sight for Euro-DOCSIS usage, saved the cost of redesigning eDOCSIS front-end.
- Reduced STB BOM cost by leveraging usage of high volume PC Ethernet device with FPGA PCI mini-bridge.
- FPGA: Common Interface (CI) hardware for DVi3000 DVB-CI Conditional Access Module (CAM).
- FPGA: MIPS-bridge, interleaved dual speed 68K bus emulation; memory re-map, interrupt priority and status.
- CPLD: ‘Fly-by-DMA’ 4x Accelerated LSI(C-Cube) back-end data throughput speed; Cable modem to Ethernet port.
- Patent U.S. 6119053, Vending Machine Dual Bus Architecture
- ‘SuperController’, next generation Vending Machine Controller (VMC); embedded PowerPC based design supporting advanced features: interactive vending, touch-screen, data communications. Lattice Semi./Synario FPGA’s provided16-bit ISA emulation/expansion via standard PC cards. Multimedia MPEG streaming from PATA/IDE storage to ISA/VGA display.
- Gas Island project, networked vending machines to the Point of Sale (POS) system for impulse credit card transactions.
- Radio-Frequency IDentification (RFID) key-fob/scanner enabled non-cash transactions with networked vendors.
- Microchip/PIC/MPLab microcontroller based VMC for the Transportation Vendor, an innovative low cost vendor for buses.
- Hardware/Firmware: Microchip/PIC re-programmable lapel pin sleeps for 6 months, blinks an LED upon hearing a jingle.