TECHNICAL SKILLS:

• Hardware design tools: DMM, Oscilloscope, Logic Analyzer, Logic Probe, and Emulators. Allegro.
• Analog circuit and digital circuit design.
• Operating Systems: Familiar with Unix/Linux Red Hat and Centos, Window, DOS.
• Scripting Languages: TCL/TK, Python, C Programming.
• Traffic Generators: IXIA, Smartbit, Agilent, Spirent
• Strong in Windows and Python batch scripting
• Jenkins experience.
• Able to debug / troubleshoot on chips, boards, and system levels.
• FPGAs evaluated on Xilinx and Altera.

PROFESSIONAL EXPERIENCE:

Confidential

Responsibilities:

• Optical Transceiver: PSM4/CWDM4
• Validating and qualifying the modules and stations on 100G CFP, CFP2, CFP4, QSFP28 of the protocols SONET/SDH, Fiber channel (FC), Optical Transport Network (OTN).
• Setting up Test stations and Designing fixtures for Test.
• Based on firmware specification of 100Gbps QSFP28, PSM4 and CLR4 transceiver modules, verifying memory map, bootloader, memory map fields for target power variation over temperature, calibration for host voltage monitor and verifying start - up sequencing of peripherals, soft start of lasers, and initial biasing of the optical modulator, initial configuration to the Tx and Rx chips, and CDRs, I2C requests and hardware line changes from the host via the QSFP management interface, Control loops, fault conditions.
• Qualifying the 100G PSM4/CLR4 modules using JDSU Traffic Test through Cisco/Arista switches
• Verifying the EEPROM and Firmware per customer.
• Using CWDM Spectrum Analyzer-Solid Optics, Multichannel Optical Power Meter-OptoTest OP710, Dicon 4 slots-GP750, Tunable Semiconductor Laser- Santec-TSL-510,

Confidential

Responsibilities:

• Working on the Apollo emulation systems based on the Sea Coast chip technology.
• Validating and verifying the engineering design.
• Bringing up and debugging and root causing the component, board to system level.
• Performing the environmental stress on board and system level on the Window and Linux environments.
• Writing test plan and test report.

Confidential

Sr. Test Engineer

Responsibilities:

• Worked as a Validation and Engineering Design Verification Test and reviewed specifications, block diagrams, schematics and BOMs, revision histories, component stress analysis, nominal and worse case environments, stability analysis, 4 corners, min-max capacitances, circuit calculations, power dissipations and worse case analysis.
• Worked closely with design, diagnostics and CM as NPI project team.
• Brought up and debugged the NPI products from component to system level to root-cause the issues using DMMs, Oscilloscopes, Logic Analyzers, Traffic Generators and Allegro tool and Diagnostics.
• Isolated the failed components, boards and systems in NPI process issues, diagnostics issues or hardware issues.
• Initiated to resolve issues and following up the bugs which had not solved yet.
• Filed bugs or feature requests to improve the coverage.
• Captured all measurements in test plan (voltages, timing, jitter, setup, hold).
• Performed and duplicated the failure analysis on units failing on field or customer return and Worked on signal integrity measurement and supported the engineering hardware design, software, Diagnostics, QA, Escalation teams.
• Analyzed and collected the failure data to feedback to the functional engineering teams Developed and documented the processes or procedures with the approval from team project members such as the bring-up test plan, SI test plan, how to bring up the prototype boards, how to debug board failures.
• Drove the closed loop corrective actions in the engineering teams relating to hardware, software, process and manufacturing issues.
• Analyzed failures on component, board, and system level by using hardware and software tool.
• Reviewed the PRR ( Pilot Readiness Review ) and the ORR ( Operational Readiness Review )
• Writing the weekly reports and test reports.

Confidential, San Jose, CA

Sr. Test Engineer

Responsibilities:

• Worked in Data Center (UCS) team as a validation, EDVT and PVT (process, voltage margins, temperature) on chip qualifications and NPI systems.
• Configured and supported Cisco routers and switches on following protocols: L2 features and EIGRP, OSPF, BGP, other IOS features
• Worked on several Cisco equipment including:2500, 2600,2800, 3800, 7200, GSR, CRS-1, CRS-3 series routers and 3K series catalyst switches.
• Developed test automation for regression testing of Cisco servers, Routers, Switches on the Linux environment.
• Worked on The San Luis 2-socket Rack-Mount Servers which are stand-alone 1U or 2U chassis, designed to operate both in standalone environments and as part of the Cisco Unified Computing System used standard x86 based 19” rack servers and used 2 Intel Romley generation processor sockets, and 24 standard DDR3 DIMM sockets. The motherboard accommodated 2 PCI-Express riser connectors, which provide slots for “full height” and “half height” PCI-e adapters, supports 2.5”HDDs through HDD backplanes, again the 1U and 2U versions with different numbers of HDDs, dual 1G-Ethernet ports (1GE LoM), a single 1GbE management port, as well as a configurable LOM card, KVM functionality given both at the front and the rear of the products.
• Provided a Manufacturing Readiness Report (MRR) before FCS.
• Reviewed specifications, block diagram, schematic and BOM, revision history, component stress analysis, nominal and worse case environments, stability analysis, 4 corner, min-max capacitance, circuit calculations, power dissipation and worse case analysis.
• Performed Test Lead on NPI projects.
• Brought up and debugged the host server products and supported the engineering lab.supported hardware design, software, Diagnostics, QA teams as Hardware Engineering worked in ESTG Escalation team interfacing with Engineering and CA to improve the quality and customer satisfactions of ESTG products by working on software and hardware defects.
• DFT by using Fault Inserting automation to test coverage for the component level and system level in order to mitigate the risk and using the test scripts to automate the environmental testing.
• Worked with Mechanical Engineering team to design the fixture for functional testing.
• Drove quality back into the Engineering organization.
• Worked on Tele-present product at Confidential such as the Lago main board consisted of a processor section, a video-backend section and audio section.
• Developed on EDVT to find the root causes and mitigate the risks.
• Wrote test plans for EDVT testing to duplicate the failures in fields.
• Performed failure analysis on the units failing on field or customer return.
• Worked on signal integrity measurement.
• Debugged on hardware and software to root cause the issues.
• In depth understanding of firmware algorithms used in any NAND Flash based storage devices (SSD, eMMC, SD, USB Flash drives) or other storage device.
• Analyzed and collected the failure data to feedback to the functional engineering teams.
• Droved the close loop corrective actions in engineering teams such as hardware and software design, process, manufacturing teams.
• Developed and documented the processes and procedures with the approval from team and project members such as the bring-up Test Plan, SI measurement Test Plan, how to bring up prototype boards, how to debug board failures, and how to track boards.
• Wrote the weekly report and test report.

Confidentian, San Jose, CA

Optical Test Engineer

Responsibilities:

• Worked on StrataLight 40Gbps DWDM transport line card with modulation scheme such as Atlas, Redstone on 260, 700 and 800 level. StrataLight's 40 Gbps transponder technology supports long-haul transmission using EDFA-only or ultra long-haul using Raman-assisted amplification.
• The line card types-Single 40/43Gbps client (aka OTS-4040), Quad 10Gbps client (aka OTS-4011), Unit-directional regenerator (aka OTS-4400). Client Interface-40/43Gbps Client, SONET/SDH, OTN, Regenerator. Optical Interface - The 40/43Gbps client interface, TX wave length: fixed, Modulation format: NRZ with Data rate, SONET/SDH mode: 39.8Gbps and Data rate, OTN mode: 43Gbps. Form Factor -The 40/43Gbps client optics pluggable form factor.
• Interfaced with manufacturing process, hardware engineers at SLC.
• Debugging or troubleshooting on board level and system level on Atlas and Redstone on 260 and 700-level to find the root-cause and feedback the issues back to process, manufacturing and component engineers to take immediately corrective actions on Sanmina and customer site.
• Collected and analyzed test yield data by Pareto Diagrams in Excel.
• Developed test plans for New Production Instruction (NPI) for several products simultaneously and under very challenging timeliness.
• Reviewed customer-provided documentation for completeness and consistency and generating required test documentation.
• Worked with engineers at SLC to set up test stations 260, 700 and 800 level on Sanmina site. Single 40/43Gbps client (aka OTS-4040), Quad 10Gbps client (aka OTS-4011), Unit-directional regenerator (aka OTS-4400), 40Gbps transponder vendors’ SFPs and QFSPs such as Finisar, OpNext, CoreOptics, Wuhan Telecommunication Devices.
• Calibrated StrataLight OTS-4000 DPSK Line Card 700 Level Test Bed.
• Provided training to Jr. Test Engineer and test technicians.

Confidential, San Jose, CA

Sr. Test Engineer

Responsibilities:

• Qualified and verified Marvell and Broadcom Gigabit Ethernet Transceivers on Cisco 2K and 3K Switch products complied with IEEE standard using Scopes, Probes, Power Modules, Analyzers, Jitter measurement tools, Generators-Pulse, Function, Traffic Generators, Hypot and CDE, Test Jigs 10/100/1000 IEEE
• Developed on Fault Insertion in order to find bugs on hardware, diagnostics, and IOS.
• Developed on EDVT to find the root causes and mitigate the risks.
• Wrote test plans
• Brought up and test prototype boards
• Debugged and troubleshot the failed boards as necessary
• Provided weekly status to the team
• Integrated the systems as needed.
• Distributed boards or systems to the team projects per schedule.
• Trained the other Test Engineer as needed

Confidential, Milpitas, CA

Sr. Test Engineer

Responsibilities:

• Diagnosed PCB failures to components level using 16500B Logic Analyzer,
• 1-Ghz TDS Digitizing Oscilloscope, DMM, etc.
• Ensured adherence to corporate quality standards and customer quality requirements.
• Collected, analyzed, monitored quality data and report, delineated between components and process issues.
• Supported Production and executed the OEM of ISO 9002.
• Worked on Project such as DELL COMPUTER and EXTREME NETWORKING.
• Implemented and maintained troubleshooting equipment and test and diagnostic software programs.
• Designed test fixtures as needed and programmed test equipment and/or developed test strategies and process for products being introduced to production.
• Developed Test Process Instruction documentations to establish test requirements and processes.
• Interfaced with other engineering functions, and possibly customers, to resolve test yield and test time issues as required, make recommendation to improve processes for testability.
• Interfaced with functional owners on quality (CFT) and with customers on customer-related issues.

Confidential, Sunnyvale, CA

Test Engineer:

Responsibilities:

• Developed the test program on Caesar tester to characterize DC, AC, and Logical functional on PCI9060, PCI9080, bus interface chips.
• Verified design specifications by using Cadence and Synopsis tools.
• Used 16500B Logic Analyzer and 500Mhz TDS Digitizing Oscilloscopes to verify Errata
• Generated Waveforms for Blue Book by conversion of VCD files to Timing Diagram.
• Familiar with Intel 80960 Family, MPC860, Power PC40x Family, Power PC60x Family and PCI Local Bus Specification Revision 2.1 & 2.2.