Systems Test Engineer Resume New jersey NJ - Hire IT People

Experienced high-speed digital CMOS digital design Engineer using Verilog / RTL design methodology. Experienced in lab bring-up, debug and hardware testing of IBM High-End Blade & ITE Servers. Very detailed and meticulous work ethic. Excellent communicator and team player.

EXPERIENCE

Confidential, Engineer (Contract Engineer) November 2011 to March 2012

Assist in building burn-in rack for testing and stressing PC build's.
Bring-up & Debug PC's.

Confidential, Blade & ITE Server Bring-up Engineer (Contract Engineer) October 2009 to November 2011

Perform hardware bring-up & debug of blade and ITE servers.
Worked closely with Power Engineer to take Power & Thermal measurements.
Take Power Measurements using oscilloscopes and meters.
Worked with TPMD & Processor Characterization
Write up & track defects.
Use Allegro & Concept to debug defects.

Confidential, Tier 1 CPU Tech Support January 2009 to October 2009

Level 1 Tech Support
Desktop / Notepad Support
Wireless Support

Confidential, Systems Test Engineer (Contract Engineer) October 2007 to October 2008

Perform system test on high end IBM Servers.
Using the HTX System Test exerciser in validation.
Includes testing on Memory, L2/L3 Cache & Service Processors.
Installed and upgraded code levels for Firmware, Microcode, AIX and HMC on high end IBM Servers.

Confidential, Digital Design Engineer June 2001 to May 2007
Design team member for cache controller (Isis) in a scalable CSI x86 Intel based SMP system.

Developed and implemented micro-architecture for data array module using Verilog (RTL)
Designed data array module using Verilog.
Debugged and verified design using unit test bench.
Assisted verification engineer with full suite of testing, including corner cases.

Design team member for cache controller (Horus) in a scalable hypertransport x86 AMD Opteron based SMP system.

Developed and implemented micro-architecture for local and remote receivers.
Designed local and remote receivers module in Verilog (RTL).
Worked with verification engineer to fully debug design.
Met timing with aggressive logic design restructure, synthesis and constraints based placement for 400Mhz version of the design.
Assisted Backend engineers with place and route.

Confidential, Digital Design Engineer June 2000 to June 2001
Design cable docsis module with VOIP.

Designed VOIP module using Xilinx FPGA's

Confidential, Various positions of increasing responsibility in Digital Design June 1978 to June 2000
Design team member for graphics adapters.

Developed and implemented micro-architecture for perspective divide logic.
Designed RTL for perspective divide using VHDL.
Debugged and verified design.

Team lead GXT800P PCI graphics adapter.

Responsible for card logic.
Responsible for programmable logic for AMD FPGA.
Integrated AMD MACH210 device for both GXT500P and GXT800P graphics adapters into one common part number, reducing the need for two different part numbers.
Card bring-up.

Design team member for IBM Ruby program.

Responsible for board programmable logic.
Responsible for board layout.
Card bring-up.

Design team member for IBM 6095 graphics workstation.

Developed and implemented micro-architecture for area fill logic.
Created sophisticated algorithm for interfacing to two DRAM memory banks - one fill plane and one boundary plane.
Logic entry using 'ceids' gate entry tool.
Verified logic using test cases.

Design team member for IBM 3270 PC.

IBM PC - X86 platform
Developed and implemented micro-architecture for I/O and memory

Decode logic.

Card logic using TI TTL logic for I/O and memory decode logic.
Turned TTL logic into Toshiba Gate Array.
Responsible for debugging card logic and bringing up cards.

SKILLS

Design Languages: Verilog, VHDL, CUPL
Programming Languages: TCL
Simulation Tools: Versim

Education:

BEEE

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Systems Test Engineer Resume

New Jersey, NJ

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