Embedded Engineer Resume

SUMMARY:

Graduate Electrical and Electronics Engineering student actively seeking for Internship/Co - op opportunities/Full-time opportunities in VLSI domain ASIC/FPGA/SoC/Design/Verification/Validation/Physical Design/UVM.

TECHNICAL SKILLS:

RTL Design, ASIC/FPGA Design, Optimization, Synthesis, Post-Synthesis, Verification, Static Timing Analysis, Design For Test (DFT), Power Analysis, Place and Route, Computer Architecture, Pipelining, Embedded Systems Development and Testing
Programming/Scripting Languages: Verilog, VHDL, C, Python, Perl, Embedded C, Assembly Language
EDA Tools: Synopsys VCS, Synopsys Design Compiler, Synopsys Design vision, GTKWave, NC-Verilog, ModelSim, Cadence Virtuoso, Cadence Encounter
Protocols: CAN, I2C, UART, AMBA, USB
Software Tools: Keil, AVR studio, Visual C++, Eclipse, FlashMagic, ECU Spectrum, Subversion, QAC
Lab equipments:: Oscilloscope, Logic Analyzers, Spectrum Analyzer
Operating Systems: Linux/ UNIX, MAC, Android, Windows

PROFESSIONAL EXPERIENCE:

Embedded Engineer

Confidential

Responsibilities:

Successfully designed and implemented 32 point IFFT algorithm including 5 stages butterfly structure using Verilog.
Performed RTL level coding, static timing analysis, circuit simulation, optimization and synthesis using VCS, Synopsys Design Compiler and Synopsys Design Vision.
Synthesis and Validation of a design to operate on 250Mhz and 333Mhz clock frequency SJSU (Verilog, Perl) Spring 2017
Modified the design for optimization and pipelining of long paths to meet given timing constraints and operate on 250Mhz as well as 333Mhz clock frequency.
Implemented on Synopsys Design Compiler using Verilog, Perl script and performed place and route using Cadence Encounter tool.

Embedded Engineer

Confidential

Responsibilities:

Developed 5-stage pipelined IEEE SP FP adder in Verilog using ModelSim and in C using visual C++.
Worked on RTL level coding, circuit simulation, optimization and static timing analysis using VCS.

Embedded Engineer

Confidential

Responsibilities:

Implemented ALU unit based on any desired addition/subtraction algorithm in Verilog using Synopsys VCS.
Analyzed for four important metrics: number of clock cycles & clock period, total time delay of an operation (multiplying/dividing), circuit area, and power consumption.
Performed RTL level coding, circuit simulation, optimization, Static timing analysis, Power analysis, synthesis and post-synthesis using VCS, Synopsys Design Compiler and Synopsys Design vision.

Embedded Engineer

Confidential

Responsibilities:

Programmed AVR Tiny2313 using Assembly language and C for connecting a biometric sensor to a relay connected to vehicle ignition system. The algorithm was developed to compare fingerprints with stored fingerprints of a valid user.
In a case of valid authentication, a signal was sent to the relay to turn on the ignition.

Embedded Engineer

Confidential

Responsibilities:

Responsible for Requirement Analysis, Design, Configurations, Embedded C Development and Testing .
Experienced in test cases preparation, compilation, testing, debugging and bug fixing.
Implemented modules: Watchdog Timer (WDG), PORT, and Micro controller Unit (MCU) in Micro controller Abstraction layer (MCAL) of Automotive Open System Architecture (AUTOSAR) project.
Designed Low Level Drivers: PORT, Micro controller Unit (MCU) and ADC for SKI BAIC Power Train project.
Acquired good knowledge of 16/32 bit Micro-controllers and used it in MCAL and SKI projects.

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