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Co-founder & Principal  Resume

San Jose, CA


  • Several years of Software Engineering experience in Development and Quality Assurance (QA).
  • Extensively worked with Programming Languages such as C/C++ and Python. Well Experienced with Object Oriented Programming, Design Patterns, and Data Structures & Algorithms.
  • Project Leader who has lead Teams and delivered Projects successfully and on time.
  • Proficient in Electronic Design Automation, Computer Networking, and Embedded Software.
  • Did Test Automation using Test - Automation-Frameworks as well as Test Automation Framework Development. Supervised creation of Regression systems.


Operating Systems: UNIX (Linux, Solaris, HPUX, AIX), Windows, Android, webOS, iOS

Languages: C, C++, Python, Perl, System Verilog, e, VHDL, Bourne Shell, C Shell, TCL, Java, HTML, XML, JSON, SQL

API: C-standard library, C++ STL, Boost, Pthreads, OpenMp, Verilog PLI & VPI, TK, QT

Tools: Flex, Bison, Make, Compilers, Debuggers, SQLite, MySQL, CVS, Subversion, Git, Purify, Purecov, Valgrind, gprof, Quantify, Sed, Awk, Apache, Google Test Framework, MS Office, Oracle Virtual Box Manager, Pylint, Doxygen, Wing IDE, Pycharms


Confidential, San Jose, CA

Co-Founder & Principal


  • Worked with a Customer on Test Framework Development using Python. Used Multiple Inheritance, Decorators, Method overloading and extension, all built-in Data types, Exceptions and various modules in Python to create a Test Automation Framework which was used by Worldwide Firmware Testing Organizations for validation of Firmware for Solid State Drives. Did debugging of Python code and used Pylint and Doxygen to check quality of the code.
  • Worked with a Customer to develop Object-Oriented code in Python to automate testing of webOS (Operating System similar to Android) for Smart Phone, Smart TV, and Virtual machine (running as an Emulator). Worked on WiFi, Bluetooth, Boot up, SSH, etc. Developed client/server model to test 2-way Bluetooth pairing using a device such as Raspberry PI, and automated the control of Power-Switch using SNMP protocol.
  • Worked with a Customer to improve performance of their C++ Behavioral Model of System-on-Chip, added interrupt modeling feature, profiled code for measuring performance, resolved run time crashes, provided work around for compiler bugs, used and evaluated Pthreads and OpenMp.
  • Worked as Senior Professional in R&D Team on Design analysis & traversal, and writing/reading of Design Databases. Architect-ed and implemented: a) Finite-State-Machine (FSM) recognition & checking technology, and capability for Graphical Viewing b) a new multi cycle Path Analysis Engine.
  • Worked as a Senior Professional in R&D Team, as a Consultant and Employee, on a Lint Software Product. Architect-ed and implemented new structural & FSM rules and supported System Verilog constructs. Fixed many bugs and added enhancements. Improved code coverage with Purecov, and validated software with Purify.

Chief Architect


  • Worked on a Software Product for Power Profiling of FPGAs using innovative Hardware/Software techniques. Responsible for overall architecture and algorithms development, and code development in C++. Reviewed team members' work done in Java and C++.
Confidential, San Jose, CA

Senior Member of Consulting Staff


  • Project Leader of eAnalyzer, a software analysis tool for e programs; e is an aspect and object-oriented Hardware Verification language. Lead Design, Development, and Implementation of analysis techniques and did their integration with the Parser and GUI; resolved issues with the tool; did development and maintenance of the Regression Test-suite; and was the primary R&D contact. Most of the implementation was done in C++ using STL; integrated rule files of flex/bison with C++, and some coding was also done in e to leverage Specman technology. The main Software Development platform was Linux, and later ported the product to Solaris, HPUX, and AIX platforms. Also, lead Surelint, an advanced Lint tool for Verilog Designs.
  • Worked on the Distributed Processing feature for a Software product. Did network programming to communicate between processes on Linux machines using TCP/IP sockets. Improved interoperability between C++ and Python components using Boost's Python Library.
  • Developed features for Scenario Builder, a GUI Product to quickly create scenarios in e, such as: compute checksum, represent and modify objects in the GUI, check syntax & semantics, etc. Coding was done in e and TCL/TK.
Confidential, San Jose, CA

Senior Software Engineer


  • Designed and Implemented an algorithm to control co-simulation between a Verilog Simulator and an Ikos Emulator using Verilog Simulator's C interfaces namely PLI and VPI, C++ STL, and Rogue Wave library.
  • Developed an API in C for the Emulator as part of a team. Did code reviews and unit testing of the API. Used PCI Device Driver routines in the C API to communicate with the Emulator.
Confidential, San Jose, CA

Senior CAD Engineer


  • Developed Library Models for Sunrise, Synopsys' Design for Testability tool. Developed tools to generate Standard cell and Memory models. Coding was done in C/Lex and Perl.
  • Maintained and Supported Logic and Memory libraries. Evaluated third-party CAD tools used in Timing Analysis, Synthesis, and Simulation. Trained and supported Field Engineering and Marketing on in-house and third-party CAD tools.
Confidential, Milpitas, CA

Senior Software QA Engineer


  • Developed tools to analyze timing data of Logic libraries. Developed tools to check the consistency of Logic, Schematic, and Layout libraries. Coding was done in C and Perl.
  • Authored Test plans which included Test items and Test strategies, and then executed them for validating LSI's Design Tools. Improved quality of products by manual and automated testing.
  • Wrote UNIX shell scripts to automate the release of Product Toolkits and do configuration checking of CAD tools and Libraries. Worked with Release Team to ensure that Products were released in a timely manner.

Publication: Paper published and presented at an IEEE conference on Fault and Defect Tolerance at Dallas, Texas in 1992, and attended several other conferences.

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